--USE work.bv_arithmetic.all; --USE std.textio.all; ENTITY mult_test IS END mult_test; ARCHITECTURE rtl OF mult_test IS CONSTANT word_size : natural := 32; SUBTYPE word IS bit_vector(word_size-1 downto 0); SIGNAL clk : bit; SIGNAL load : bit; SIGNAL multiplicand : word; SIGNAL multiply_by : word; SIGNAL ready : bit; SIGNAL product_low : word; SIGNAL product_high : word; SIGNAL b : word; SIGNAL b_or_0 : word; SIGNAL partial_product : word; SIGNAL c_in : bit; SIGNAL c_out : bit; SIGNAL c_to_p : bit; SIGNAL p_to_a : bit; SIGNAL p_and_c_load : bit; SIGNAL shift : bit; SIGNAL tied_0 : bit := '0'; ALIAS a_0 : bit IS product_low(0); SIGNAL c : bit_vector(31 downto 1); BEGIN -- bench --UUT : multiplier -- port map ( clk, load, multiplicand, multiply_by, -- ready, product_low, product_high); ---------------------------------------------------------------- --a_reg : shift_reg_word -- port map ( clk => clk, -- load => load, -- shift => shift, -- clr => tied_0, -- d => multiplicand, -- d_s => p_to_a, -- q => product_low, -- q_s => open ); --a_reg : PROCESS (clk) -- CONSTANT Tpd_clk_q_clr : Time := 4 ns; -- CONSTANT Tpd_clk_q_load : Time := 5 ns; -- CONSTANT Tpd_clk_q_shift : Time := 6 ns; -- VARIABLE reg_value : word; --BEGIN -- PROCESS a_reg -- IF (clk = '1') THEN -- IF (tied_0 = '1') THEN -- reg_value := word'(others => '0'); -- product_low <= reg_value after Tpd_clk_q_clr; -- --q_s <= reg_value(0) after Tpd_Clk_Q_clr; -- ELSIF (load = '1') THEN -- reg_value := multiplicand; -- product_low <= reg_value after Tpd_clk_q_load; -- --q_s <= reg_value(0) after Tpd_Clk_Q_Load; -- ELSIF (shift = '1') THEN -- FOR i IN 1 TO word_size-1 LOOP -- reg_value(i-1) := reg_value(i); -- END LOOP; -- i -- reg_value(word_size-1) := p_to_a; -- product_low <= reg_value after Tpd_clk_q_shift; -- --q_s <= reg_value(0) after Tpd_Clk_Q_shift; -- END IF; -- END IF; --END PROCESS a_reg; a_reg_31 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(31) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(31); product_low(31) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := p_to_a; product_low(31) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_31; a_reg_30 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(30) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(30); product_low(30) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(30+1); product_low(30) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_30; a_reg_29 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(29) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(29); product_low(29) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(29+1); product_low(29) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_29; a_reg_28 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(28) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(28); product_low(28) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(28+1); product_low(28) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_28; a_reg_27 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(27) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(27); product_low(27) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(27+1); product_low(27) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_27; a_reg_26 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(26) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(26); product_low(26) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(26+1); product_low(26) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_26; a_reg_25 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(25) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(25); product_low(25) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(25+1); product_low(25) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_25; a_reg_24 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(24) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(24); product_low(24) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(24+1); product_low(24) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_24; a_reg_23 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(23) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(23); product_low(23) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(23+1); product_low(23) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_23; a_reg_22 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(22) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(22); product_low(22) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(22+1); product_low(22) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_22; a_reg_21 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(21) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(21); product_low(21) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(21+1); product_low(21) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_21; a_reg_20 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(20) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(20); product_low(20) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(20+1); product_low(20) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_20; a_reg_19 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(19) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(19); product_low(19) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(19+1); product_low(19) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_19; a_reg_18 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(18) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(18); product_low(18) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(18+1); product_low(18) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_18; a_reg_17 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(17) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(17); product_low(17) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(17+1); product_low(17) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_17; a_reg_16 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(16) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(16); product_low(16) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(16+1); product_low(16) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_16; a_reg_15 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(15) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(15); product_low(15) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(15+1); product_low(15) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_15; a_reg_14 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(14) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(14); product_low(14) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(14+1); product_low(14) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_14; a_reg_13 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(13) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(13); product_low(13) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(13+1); product_low(13) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_13; a_reg_12 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(12) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(12); product_low(12) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(12+1); product_low(12) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_12; a_reg_11 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(11) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(11); product_low(11) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(11+1); product_low(11) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_11; a_reg_10 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(10) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(10); product_low(10) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(10+1); product_low(10) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_10; a_reg_9 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(9) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(9); product_low(9) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(9+1); product_low(9) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_9; a_reg_8 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(8) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(8); product_low(8) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(8+1); product_low(8) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_8; a_reg_7 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(7) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(7); product_low(7) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(7+1); product_low(7) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_7; a_reg_6 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(6) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(6); product_low(6) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(6+1); product_low(6) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_6; a_reg_5 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(5) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(5); product_low(5) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(5+1); product_low(5) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_5; a_reg_4 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(4) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(4); product_low(4) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(4+1); product_low(4) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_4; a_reg_3 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(3) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(3); product_low(3) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(3+1); product_low(3) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_3; a_reg_2 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(2) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(2); product_low(2) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(2+1); product_low(2) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_2; a_reg_1 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(1) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(1); product_low(1) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(1+1); product_low(1) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_1; a_reg_0 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; BEGIN -- PROCESS a_reg IF (clk = '1') THEN IF (tied_0 = '1') THEN reg_value := '0'; product_low(0) <= reg_value after Tpd_clk_q_clr; ELSIF (load = '1') THEN reg_value := multiplicand(0); product_low(0) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_low(0+1); product_low(0) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS a_reg_0; ---------------------------------------------------------------- --b_reg : reg_word -- port map ( clk => clk, -- load => load, -- d => multiply_by, -- q => b ); --b_reg : PROCESS (clk) -- CONSTANT Tpd_clk_q : Time := 4 ns; --BEGIN -- PROCESS b_reg -- IF (clk = '1' AND load = '1') THEN -- b <= multiply_by after Tpd_clk_q; -- END IF; --END PROCESS b_reg; b_reg_0 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_0 IF (clk = '1' AND load = '1') THEN b(0) <= multiply_by(0) after Tpd_clk_q; END IF; END PROCESS b_reg_0; b_reg_1 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_1 IF (clk = '1' AND load = '1') THEN b(1) <= multiply_by(1) after Tpd_clk_q; END IF; END PROCESS b_reg_1; b_reg_2 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_2 IF (clk = '1' AND load = '1') THEN b(2) <= multiply_by(2) after Tpd_clk_q; END IF; END PROCESS b_reg_2; b_reg_3 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_3 IF (clk = '1' AND load = '1') THEN b(3) <= multiply_by(3) after Tpd_clk_q; END IF; END PROCESS b_reg_3; b_reg_4 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_4 IF (clk = '1' AND load = '1') THEN b(4) <= multiply_by(4) after Tpd_clk_q; END IF; END PROCESS b_reg_4; b_reg_5 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_5 IF (clk = '1' AND load = '1') THEN b(5) <= multiply_by(5) after Tpd_clk_q; END IF; END PROCESS b_reg_5; b_reg_6 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_6 IF (clk = '1' AND load = '1') THEN b(6) <= multiply_by(6) after Tpd_clk_q; END IF; END PROCESS b_reg_6; b_reg_7 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_7 IF (clk = '1' AND load = '1') THEN b(7) <= multiply_by(7) after Tpd_clk_q; END IF; END PROCESS b_reg_7; b_reg_8 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_8 IF (clk = '1' AND load = '1') THEN b(8) <= multiply_by(8) after Tpd_clk_q; END IF; END PROCESS b_reg_8; b_reg_9 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_9 IF (clk = '1' AND load = '1') THEN b(9) <= multiply_by(9) after Tpd_clk_q; END IF; END PROCESS b_reg_9; b_reg_10 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_10 IF (clk = '1' AND load = '1') THEN b(10) <= multiply_by(10) after Tpd_clk_q; END IF; END PROCESS b_reg_10; b_reg_11 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_11 IF (clk = '1' AND load = '1') THEN b(11) <= multiply_by(11) after Tpd_clk_q; END IF; END PROCESS b_reg_11; b_reg_12 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_12 IF (clk = '1' AND load = '1') THEN b(12) <= multiply_by(12) after Tpd_clk_q; END IF; END PROCESS b_reg_12; b_reg_13 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_13 IF (clk = '1' AND load = '1') THEN b(13) <= multiply_by(13) after Tpd_clk_q; END IF; END PROCESS b_reg_13; b_reg_14 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_14 IF (clk = '1' AND load = '1') THEN b(14) <= multiply_by(14) after Tpd_clk_q; END IF; END PROCESS b_reg_14; b_reg_15 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_15 IF (clk = '1' AND load = '1') THEN b(15) <= multiply_by(15) after Tpd_clk_q; END IF; END PROCESS b_reg_15; b_reg_16 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_16 IF (clk = '1' AND load = '1') THEN b(16) <= multiply_by(16) after Tpd_clk_q; END IF; END PROCESS b_reg_16; b_reg_17 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_17 IF (clk = '1' AND load = '1') THEN b(17) <= multiply_by(17) after Tpd_clk_q; END IF; END PROCESS b_reg_17; b_reg_18 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_18 IF (clk = '1' AND load = '1') THEN b(18) <= multiply_by(18) after Tpd_clk_q; END IF; END PROCESS b_reg_18; b_reg_19 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_19 IF (clk = '1' AND load = '1') THEN b(19) <= multiply_by(19) after Tpd_clk_q; END IF; END PROCESS b_reg_19; b_reg_20 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_20 IF (clk = '1' AND load = '1') THEN b(20) <= multiply_by(20) after Tpd_clk_q; END IF; END PROCESS b_reg_20; b_reg_21 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_21 IF (clk = '1' AND load = '1') THEN b(21) <= multiply_by(21) after Tpd_clk_q; END IF; END PROCESS b_reg_21; b_reg_22 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_22 IF (clk = '1' AND load = '1') THEN b(22) <= multiply_by(22) after Tpd_clk_q; END IF; END PROCESS b_reg_22; b_reg_23 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_23 IF (clk = '1' AND load = '1') THEN b(23) <= multiply_by(23) after Tpd_clk_q; END IF; END PROCESS b_reg_23; b_reg_24 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_24 IF (clk = '1' AND load = '1') THEN b(24) <= multiply_by(24) after Tpd_clk_q; END IF; END PROCESS b_reg_24; b_reg_25 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_25 IF (clk = '1' AND load = '1') THEN b(25) <= multiply_by(25) after Tpd_clk_q; END IF; END PROCESS b_reg_25; b_reg_26 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_26 IF (clk = '1' AND load = '1') THEN b(26) <= multiply_by(26) after Tpd_clk_q; END IF; END PROCESS b_reg_26; b_reg_27 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_27 IF (clk = '1' AND load = '1') THEN b(27) <= multiply_by(27) after Tpd_clk_q; END IF; END PROCESS b_reg_27; b_reg_28 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_28 IF (clk = '1' AND load = '1') THEN b(28) <= multiply_by(28) after Tpd_clk_q; END IF; END PROCESS b_reg_28; b_reg_29 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_29 IF (clk = '1' AND load = '1') THEN b(29) <= multiply_by(29) after Tpd_clk_q; END IF; END PROCESS b_reg_29; b_reg_30 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_30 IF (clk = '1' AND load = '1') THEN b(30) <= multiply_by(30) after Tpd_clk_q; END IF; END PROCESS b_reg_30; b_reg_31 : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS b_reg_31 IF (clk = '1' AND load = '1') THEN b(31) <= multiply_by(31) after Tpd_clk_q; END IF; END PROCESS b_reg_31; ---------------------------------------------------------------- --p_reg : shift_reg_word -- port map ( clk => clk, -- load => p_and_c_load, -- shift => shift, -- clr => load, -- d => partial_product, -- d_s => c_in, -- q => product_high, -- q_s => p_to_a ); --p_reg : PROCESS (clk) -- CONSTANT Tpd_clk_q_clr : Time := 4 ns; -- CONSTANT Tpd_clk_q_load : Time := 5 ns; -- CONSTANT Tpd_clk_q_shift : Time := 6 ns; -- VARIABLE reg_value : word; --Begin -- PROCESS p_reg -- IF (clk = '1') THEN -- IF (load = '1') THEN -- reg_value := word'(others => '0'); -- product_high <= reg_value after Tpd_clk_q_clr; -- p_to_a <= reg_value(0) after Tpd_Clk_Q_clr; -- ELSIF (p_and_c_load = '1') THEN -- reg_value := partial_product; -- product_high <= reg_value after Tpd_clk_q_load; -- p_to_a <= reg_value(0) after Tpd_Clk_Q_Load; -- ELSIF (shift = '1') THEN -- FOR i IN 1 TO word_size-1 LOOP -- reg_value(i-1) := reg_value(i); -- END LOOP; -- i -- reg_value(word_size-1) := c_in; -- product_high <= reg_value after Tpd_clk_q_shift; -- p_to_a <= reg_value(0) after Tpd_Clk_Q_shift; -- END IF; -- END IF; --END PROCESS p_reg; p_reg_31 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_31 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(31) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(31); product_high(31) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := c_in; product_high(31) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_31; p_reg_30 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_30 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(30) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(30); product_high(30) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(30+1); product_high(30) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_30; p_reg_29 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_29 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(29) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(29); product_high(29) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(29+1); product_high(29) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_29; p_reg_28 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_28 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(28) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(28); product_high(28) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(28+1); product_high(28) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_28; p_reg_27 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_27 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(27) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(27); product_high(27) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(27+1); product_high(27) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_27; p_reg_26 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_26 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(26) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(26); product_high(26) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(26+1); product_high(26) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_26; p_reg_25 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_25 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(25) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(25); product_high(25) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(25+1); product_high(25) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_25; p_reg_24 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_24 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(24) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(24); product_high(24) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(24+1); product_high(24) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_24; p_reg_23 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_23 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(23) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(23); product_high(23) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(23+1); product_high(23) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_23; p_reg_22 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_22 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(22) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(22); product_high(22) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(22+1); product_high(22) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_22; p_reg_21 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_21 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(21) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(21); product_high(21) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(21+1); product_high(21) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_21; p_reg_20 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_20 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(20) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(20); product_high(20) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(20+1); product_high(20) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_20; p_reg_19 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_19 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(19) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(19); product_high(19) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(19+1); product_high(19) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_19; p_reg_18 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_18 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(18) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(18); product_high(18) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(18+1); product_high(18) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_18; p_reg_17 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_17 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(17) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(17); product_high(17) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(17+1); product_high(17) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_17; p_reg_16 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_16 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(16) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(16); product_high(16) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(16+1); product_high(16) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_16; p_reg_15 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_15 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(15) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(15); product_high(15) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(15+1); product_high(15) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_15; p_reg_14 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_14 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(14) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(14); product_high(14) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(14+1); product_high(14) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_14; p_reg_13 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_13 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(13) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(13); product_high(13) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(13+1); product_high(13) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_13; p_reg_12 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_12 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(12) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(12); product_high(12) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(12+1); product_high(12) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_12; p_reg_11 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_11 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(11) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(11); product_high(11) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(11+1); product_high(11) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_11; p_reg_10 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_10 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(10) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(10); product_high(10) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(10+1); product_high(10) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_10; p_reg_9 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_9 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(9) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(9); product_high(9) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(9+1); product_high(9) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_9; p_reg_8 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_8 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(8) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(8); product_high(8) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(8+1); product_high(8) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_8; p_reg_7 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_7 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(7) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(7); product_high(7) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(7+1); product_high(7) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_7; p_reg_6 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_6 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(6) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(6); product_high(6) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(6+1); product_high(6) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_6; p_reg_5 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_5 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(5) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(5); product_high(5) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(5+1); product_high(5) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_5; p_reg_4 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_4 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(4) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(4); product_high(4) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(4+1); product_high(4) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_4; p_reg_3 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_3 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(3) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(3); product_high(3) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(3+1); product_high(3) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_3; p_reg_2 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_2 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(2) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(2); product_high(2) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(2+1); product_high(2) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_2; p_reg_1 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_1 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(1) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(1); product_high(1) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(1+1); product_high(1) <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_1; p_reg_0 : PROCESS (clk) CONSTANT Tpd_clk_q_clr : Time := 4 ns; CONSTANT Tpd_clk_q_load : Time := 5 ns; CONSTANT Tpd_clk_q_shift : Time := 6 ns; VARIABLE reg_value : bit; Begin -- PROCESS p_reg_0 IF (clk = '1') THEN IF (load = '1') THEN reg_value := '0'; product_high(0) <= reg_value after Tpd_clk_q_clr; ELSIF (p_and_c_load = '1') THEN reg_value := partial_product(0); product_high(0) <= reg_value after Tpd_clk_q_load; ELSIF (shift = '1') THEN reg_value := product_high(0+1); product_high(0) <= reg_value after Tpd_clk_q_shift; p_to_a <= reg_value after Tpd_clk_q_shift; END IF; END IF; END PROCESS p_reg_0; ---------------------------------------------------------------- --carry_reg : reg_1 -- port map (clk => clk, -- load => p_and_c_load, -- d => c_out, -- q => c_in ); carry_reg : PROCESS (clk) CONSTANT Tpd_clk_q : Time := 4 ns; BEGIN -- PROCESS carry_reg IF (clk = '1' AND p_and_c_load = '1') THEN c_in <= c_out after Tpd_clk_q; END IF; END PROCESS carry_reg; ---------------------------------------------------------------- --b_gate : and_word -- port map ( a => a_0, -- b => b, -- z => b_or_0 ); --b_gate: -- b_or_0 <= b WHEN a_0 = '1' -- ELSE -- word'(others => '0'); b_gate_0: b_or_0(0) <= b(0) WHEN a_0 = '1' ELSE '0'; b_gate_1: b_or_0(1) <= b(1) WHEN a_0 = '1' ELSE '0'; b_gate_2: b_or_0(2) <= b(2) WHEN a_0 = '1' ELSE '0'; b_gate_3: b_or_0(3) <= b(3) WHEN a_0 = '1' ELSE '0'; b_gate_4: b_or_0(4) <= b(4) WHEN a_0 = '1' ELSE '0'; b_gate_5: b_or_0(5) <= b(5) WHEN a_0 = '1' ELSE '0'; b_gate_6: b_or_0(6) <= b(6) WHEN a_0 = '1' ELSE '0'; b_gate_7: b_or_0(7) <= b(7) WHEN a_0 = '1' ELSE '0'; b_gate_8: b_or_0(8) <= b(8) WHEN a_0 = '1' ELSE '0'; b_gate_9: b_or_0(9) <= b(9) WHEN a_0 = '1' ELSE '0'; b_gate_10: b_or_0(10) <= b(10) WHEN a_0 = '1' ELSE '0'; b_gate_11: b_or_0(11) <= b(11) WHEN a_0 = '1' ELSE '0'; b_gate_12: b_or_0(12) <= b(12) WHEN a_0 = '1' ELSE '0'; b_gate_13: b_or_0(13) <= b(13) WHEN a_0 = '1' ELSE '0'; b_gate_14: b_or_0(14) <= b(14) WHEN a_0 = '1' ELSE '0'; b_gate_15: b_or_0(15) <= b(15) WHEN a_0 = '1' ELSE '0'; b_gate_16: b_or_0(16) <= b(16) WHEN a_0 = '1' ELSE '0'; b_gate_17: b_or_0(17) <= b(17) WHEN a_0 = '1' ELSE '0'; b_gate_18: b_or_0(18) <= b(18) WHEN a_0 = '1' ELSE '0'; b_gate_19: b_or_0(19) <= b(19) WHEN a_0 = '1' ELSE '0'; b_gate_20: b_or_0(20) <= b(20) WHEN a_0 = '1' ELSE '0'; b_gate_21: b_or_0(21) <= b(21) WHEN a_0 = '1' ELSE '0'; b_gate_22: b_or_0(22) <= b(22) WHEN a_0 = '1' ELSE '0'; b_gate_23: b_or_0(23) <= b(23) WHEN a_0 = '1' ELSE '0'; b_gate_24: b_or_0(24) <= b(24) WHEN a_0 = '1' ELSE '0'; b_gate_25: b_or_0(25) <= b(25) WHEN a_0 = '1' ELSE '0'; b_gate_26: b_or_0(26) <= b(26) WHEN a_0 = '1' ELSE '0'; b_gate_27: b_or_0(27) <= b(27) WHEN a_0 = '1' ELSE '0'; b_gate_28: b_or_0(28) <= b(28) WHEN a_0 = '1' ELSE '0'; b_gate_29: b_or_0(29) <= b(29) WHEN a_0 = '1' ELSE '0'; b_gate_30: b_or_0(30) <= b(30) WHEN a_0 = '1' ELSE '0'; b_gate_31: b_or_0(31) <= b(31) WHEN a_0 = '1' ELSE '0'; ---------------------------------------------------------------- --the_adder : adder -- port map ( a => product_high, -- b => b_or_0, -- c_in => c_in, -- s => partial_product, -- c_out => c_out ); --the_adder : PROCESS (product_high, b_or_0, c_in) -- CONSTANT Tpd : Time := 8 ns; -- VARIABLE c : bit; -- VARIABLE sum : word; --BEGIN -- PROCESS the_adder -- c := c_in; -- FOR i IN 0 to word_size-1 LOOP -- sum(i) := (product_high(i) XOR b_or_0(i)) XOR c; -- c := (product_high(i) AND b_or_0(i)) -- OR ((product_high(i) XOR b_or_0(i)) AND c); -- END LOOP; -- partial_product <= sum after Tpd; -- c_out <= c after Tpd; --END PROCESS the_adder; the_adder_0 : PROCESS (product_high(0), b_or_0(0), c_in) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_0 partial_product(0) <= (product_high(0) XOR b_or_0(0)) XOR c_in after Tpd; c(0+1) <= (product_high(0) AND b_or_0(0)) OR ((product_high(0) XOR b_or_0(0)) AND c_in) after Tpd; END PROCESS the_adder_0; the_adder_1 : PROCESS (product_high(1), b_or_0(1), c(1)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_1 partial_product(1) <= (product_high(1) XOR b_or_0(1)) XOR c(1) after Tpd; c(1+1) <= (product_high(1) AND b_or_0(1)) OR ((product_high(1) XOR b_or_0(1)) AND c(1)) after Tpd; END PROCESS the_adder_1; the_adder_2 : PROCESS (product_high(2), b_or_0(2), c(2)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_2 partial_product(2) <= (product_high(2) XOR b_or_0(2)) XOR c(2) after Tpd; c(2+1) <= (product_high(2) AND b_or_0(2)) OR ((product_high(2) XOR b_or_0(2)) AND c(2)) after Tpd; END PROCESS the_adder_2; the_adder_3 : PROCESS (product_high(3), b_or_0(3), c(3)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_3 partial_product(3) <= (product_high(3) XOR b_or_0(3)) XOR c(3) after Tpd; c(3+1) <= (product_high(3) AND b_or_0(3)) OR ((product_high(3) XOR b_or_0(3)) AND c(3)) after Tpd; END PROCESS the_adder_3; the_adder_4 : PROCESS (product_high(4), b_or_0(4), c(4)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_4 partial_product(4) <= (product_high(4) XOR b_or_0(4)) XOR c(4) after Tpd; c(4+1) <= (product_high(4) AND b_or_0(4)) OR ((product_high(4) XOR b_or_0(4)) AND c(4)) after Tpd; END PROCESS the_adder_4; the_adder_5 : PROCESS (product_high(5), b_or_0(5), c(5)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_5 partial_product(5) <= (product_high(5) XOR b_or_0(5)) XOR c(5) after Tpd; c(5+1) <= (product_high(5) AND b_or_0(5)) OR ((product_high(5) XOR b_or_0(5)) AND c(5)) after Tpd; END PROCESS the_adder_5; the_adder_6 : PROCESS (product_high(6), b_or_0(6), c(6)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_6 partial_product(6) <= (product_high(6) XOR b_or_0(6)) XOR c(6) after Tpd; c(6+1) <= (product_high(6) AND b_or_0(6)) OR ((product_high(6) XOR b_or_0(6)) AND c(6)) after Tpd; END PROCESS the_adder_6; the_adder_7 : PROCESS (product_high(7), b_or_0(7), c(7)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_7 partial_product(7) <= (product_high(7) XOR b_or_0(7)) XOR c(7) after Tpd; c(7+1) <= (product_high(7) AND b_or_0(7)) OR ((product_high(7) XOR b_or_0(7)) AND c(7)) after Tpd; END PROCESS the_adder_7; the_adder_8 : PROCESS (product_high(8), b_or_0(8), c(8)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_8 partial_product(8) <= (product_high(8) XOR b_or_0(8)) XOR c(8) after Tpd; c(8+1) <= (product_high(8) AND b_or_0(8)) OR ((product_high(8) XOR b_or_0(8)) AND c(8)) after Tpd; END PROCESS the_adder_8; the_adder_9 : PROCESS (product_high(9), b_or_0(9), c(9)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_9 partial_product(9) <= (product_high(9) XOR b_or_0(9)) XOR c(9) after Tpd; c(9+1) <= (product_high(9) AND b_or_0(9)) OR ((product_high(9) XOR b_or_0(9)) AND c(9)) after Tpd; END PROCESS the_adder_9; the_adder_10 : PROCESS (product_high(10), b_or_0(10), c(10)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_10 partial_product(10) <= (product_high(10) XOR b_or_0(10)) XOR c(10) after Tpd; c(10+1) <= (product_high(10) AND b_or_0(10)) OR ((product_high(10) XOR b_or_0(10)) AND c(10)) after Tpd; END PROCESS the_adder_10; the_adder_11 : PROCESS (product_high(11), b_or_0(11), c(11)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_11 partial_product(11) <= (product_high(11) XOR b_or_0(11)) XOR c(11) after Tpd; c(11+1) <= (product_high(11) AND b_or_0(11)) OR ((product_high(11) XOR b_or_0(11)) AND c(11)) after Tpd; END PROCESS the_adder_11; the_adder_12 : PROCESS (product_high(12), b_or_0(12), c(12)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_12 partial_product(12) <= (product_high(12) XOR b_or_0(12)) XOR c(12) after Tpd; c(12+1) <= (product_high(12) AND b_or_0(12)) OR ((product_high(12) XOR b_or_0(12)) AND c(12)) after Tpd; END PROCESS the_adder_12; the_adder_13 : PROCESS (product_high(13), b_or_0(13), c(13)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_13 partial_product(13) <= (product_high(13) XOR b_or_0(13)) XOR c(13) after Tpd; c(13+1) <= (product_high(13) AND b_or_0(13)) OR ((product_high(13) XOR b_or_0(13)) AND c(13)) after Tpd; END PROCESS the_adder_13; the_adder_14 : PROCESS (product_high(14), b_or_0(14), c(14)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_14 partial_product(14) <= (product_high(14) XOR b_or_0(14)) XOR c(14) after Tpd; c(14+1) <= (product_high(14) AND b_or_0(14)) OR ((product_high(14) XOR b_or_0(14)) AND c(14)) after Tpd; END PROCESS the_adder_14; the_adder_15 : PROCESS (product_high(15), b_or_0(15), c(15)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_15 partial_product(15) <= (product_high(15) XOR b_or_0(15)) XOR c(15) after Tpd; c(15+1) <= (product_high(15) AND b_or_0(15)) OR ((product_high(15) XOR b_or_0(15)) AND c(15)) after Tpd; END PROCESS the_adder_15; the_adder_16 : PROCESS (product_high(16), b_or_0(16), c(16)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_16 partial_product(16) <= (product_high(16) XOR b_or_0(16)) XOR c(16) after Tpd; c(16+1) <= (product_high(16) AND b_or_0(16)) OR ((product_high(16) XOR b_or_0(16)) AND c(16)) after Tpd; END PROCESS the_adder_16; the_adder_17 : PROCESS (product_high(17), b_or_0(17), c(17)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_17 partial_product(17) <= (product_high(17) XOR b_or_0(17)) XOR c(17) after Tpd; c(17+1) <= (product_high(17) AND b_or_0(17)) OR ((product_high(17) XOR b_or_0(17)) AND c(17)) after Tpd; END PROCESS the_adder_17; the_adder_18 : PROCESS (product_high(18), b_or_0(18), c(18)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_18 partial_product(18) <= (product_high(18) XOR b_or_0(18)) XOR c(18) after Tpd; c(18+1) <= (product_high(18) AND b_or_0(18)) OR ((product_high(18) XOR b_or_0(18)) AND c(18)) after Tpd; END PROCESS the_adder_18; the_adder_19 : PROCESS (product_high(19), b_or_0(19), c(19)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_19 partial_product(19) <= (product_high(19) XOR b_or_0(19)) XOR c(19) after Tpd; c(19+1) <= (product_high(19) AND b_or_0(19)) OR ((product_high(19) XOR b_or_0(19)) AND c(19)) after Tpd; END PROCESS the_adder_19; the_adder_20 : PROCESS (product_high(20), b_or_0(20), c(20)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_20 partial_product(20) <= (product_high(20) XOR b_or_0(20)) XOR c(20) after Tpd; c(20+1) <= (product_high(20) AND b_or_0(20)) OR ((product_high(20) XOR b_or_0(20)) AND c(20)) after Tpd; END PROCESS the_adder_20; the_adder_21 : PROCESS (product_high(21), b_or_0(21), c(21)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_21 partial_product(21) <= (product_high(21) XOR b_or_0(21)) XOR c(21) after Tpd; c(21+1) <= (product_high(21) AND b_or_0(21)) OR ((product_high(21) XOR b_or_0(21)) AND c(21)) after Tpd; END PROCESS the_adder_21; the_adder_22 : PROCESS (product_high(22), b_or_0(22), c(22)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_22 partial_product(22) <= (product_high(22) XOR b_or_0(22)) XOR c(22) after Tpd; c(22+1) <= (product_high(22) AND b_or_0(22)) OR ((product_high(22) XOR b_or_0(22)) AND c(22)) after Tpd; END PROCESS the_adder_22; the_adder_23 : PROCESS (product_high(23), b_or_0(23), c(23)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_23 partial_product(23) <= (product_high(23) XOR b_or_0(23)) XOR c(23) after Tpd; c(23+1) <= (product_high(23) AND b_or_0(23)) OR ((product_high(23) XOR b_or_0(23)) AND c(23)) after Tpd; END PROCESS the_adder_23; the_adder_24 : PROCESS (product_high(24), b_or_0(24), c(24)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_24 partial_product(24) <= (product_high(24) XOR b_or_0(24)) XOR c(24) after Tpd; c(24+1) <= (product_high(24) AND b_or_0(24)) OR ((product_high(24) XOR b_or_0(24)) AND c(24)) after Tpd; END PROCESS the_adder_24; the_adder_25 : PROCESS (product_high(25), b_or_0(25), c(25)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_25 partial_product(25) <= (product_high(25) XOR b_or_0(25)) XOR c(25) after Tpd; c(25+1) <= (product_high(25) AND b_or_0(25)) OR ((product_high(25) XOR b_or_0(25)) AND c(25)) after Tpd; END PROCESS the_adder_25; the_adder_26 : PROCESS (product_high(26), b_or_0(26), c(26)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_26 partial_product(26) <= (product_high(26) XOR b_or_0(26)) XOR c(26) after Tpd; c(26+1) <= (product_high(26) AND b_or_0(26)) OR ((product_high(26) XOR b_or_0(26)) AND c(26)) after Tpd; END PROCESS the_adder_26; the_adder_27 : PROCESS (product_high(27), b_or_0(27), c(27)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_27 partial_product(27) <= (product_high(27) XOR b_or_0(27)) XOR c(27) after Tpd; c(27+1) <= (product_high(27) AND b_or_0(27)) OR ((product_high(27) XOR b_or_0(27)) AND c(27)) after Tpd; END PROCESS the_adder_27; the_adder_28 : PROCESS (product_high(28), b_or_0(28), c(28)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_28 partial_product(28) <= (product_high(28) XOR b_or_0(28)) XOR c(28) after Tpd; c(28+1) <= (product_high(28) AND b_or_0(28)) OR ((product_high(28) XOR b_or_0(28)) AND c(28)) after Tpd; END PROCESS the_adder_28; the_adder_29 : PROCESS (product_high(29), b_or_0(29), c(29)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_29 partial_product(29) <= (product_high(29) XOR b_or_0(29)) XOR c(29) after Tpd; c(29+1) <= (product_high(29) AND b_or_0(29)) OR ((product_high(29) XOR b_or_0(29)) AND c(29)) after Tpd; END PROCESS the_adder_29; the_adder_30 : PROCESS (product_high(30), b_or_0(30), c(30)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_30 partial_product(30) <= (product_high(30) XOR b_or_0(30)) XOR c(30) after Tpd; c(30+1) <= (product_high(30) AND b_or_0(30)) OR ((product_high(30) XOR b_or_0(30)) AND c(30)) after Tpd; END PROCESS the_adder_30; the_adder_31 : PROCESS (product_high(31), b_or_0(31), c(31)) CONSTANT Tpd : Time := 2 ns; BEGIN -- PROCESS the_adder_31 partial_product(31) <= (product_high(31) XOR b_or_0(31)) XOR c(31) after Tpd; c_out <= (product_high(31) AND b_or_0(31)) OR ((product_high(31) XOR b_or_0(31)) AND c(31)) after Tpd; END PROCESS the_adder_31; ---------------------------------------------------------------- ----------------------------------------------------------------------------- -- Process: controller -- Purpose: sequences register loading and shifting -- Inputs: clk, load -- Outputs: p_and_c_load, shift, ready ----------------------------------------------------------------------------- controller : PROCESS CONSTANT Tpd_clk_load : Time := 5 ns; CONSTANT Tpd_clk_shift : Time := 5 ns; CONSTANT Tpd_clk_ready : Time := 5 ns; BEGIN -- PROCESS controller p_and_c_load <= '0' after Tpd_Clk_Load; shift <= '0' after Tpd_clk_shift; ready <= '1' after Tpd_clk_ready; WAIT on clk until clk = '1' and load = '1'; ready <= '0' after Tpd_clk_ready; FOR cycle IN 1 to word_size LOOP p_and_c_load <= '1' after Tpd_clk_load; WAIT until clk = '1'; p_and_c_load <= '0' after Tpd_clk_load; shift <= '1' after Tpd_clk_shift; WAIT until clk = '1'; shift <= '0' after Tpd_clk_shift; END LOOP; -- cycle ready <= '1' after Tpd_clk_ready; END PROCESS controller; ---------------------------------------------------------------- clock_gen : PROCESS CONSTANT Tc : Time := 100 ns; BEGIN -- PROCESS clock_gen FOR i IN 1 to 500 LOOP WAIT for Tc/2; clk <= '1'; WAIT for Tc - Tc/2; clk <= '0'; END LOOP; -- i wait; END PROCESS clock_gen; tester : PROCESS --VARIABLE L : line; PROCEDURE drive (a, b : word) IS CONSTANT Tdelay : Time := 6 ns; BEGIN multiplicand <= a after Tdelay; multiply_by <= b after Tdelay; load <= '1' after Tdelay; WAIT until clk = '1'; load <= '0' after Tdelay; WAIT on clk until clk = '1' and ready = '1'; END drive; BEGIN -- PROCESS tester drive(X"0000_0000", X"0000_0002"); --write(L, string'("tester: X""0"" x X""2"" -> ")); --write_hex(L, product_high); --write(L, ' '); --write_hex(L, product_low); --writeline(output, L); -- drive(X"0000_0002", X"0000_0002"); --write(L, string'("tester: X""2"" x X""2"" -> ")); --write_hex(L, product_high); --write(L, ' '); --write_hex(L, product_low); --writeline(output, L); -- drive(x"A5A5_A5A5", x"5A5A_5A5A"); --write(L, string'("tester: x""A5A5_A5A5"" x x""5A5A_5A5A"" -> ")); --write_hex(L, product_high); --write(L, ' '); --write_hex(L, product_low); --writeline(output, L); -- drive(X"FFFF_FFFF", X"FFFF_FFFF"); --write(L, string'("tester: X""FFFF_FFFF"" x X""FFFF_FFFF"" -> ")); --write_hex(L, product_high); --write(L, ' '); --write_hex(L, product_low); --writeline(output, L); -- wait; END PROCESS tester; END rtl;