-- VHDL data flow description generated from `zero_y`
--		date : Fri Jan 22 09:40:26 1993


-- Entity Declaration

ENTITY zero_y IS
  GENERIC (
    CONSTANT area : NATURAL := 504;	-- area
    CONSTANT rdown : NATURAL := 1794	-- rdown
  );
  PORT (
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END zero_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF zero_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on zero_y"
    SEVERITY WARNING;


f <= '0';
END;