-- VHDL data flow description generated from `tsn_y`
--		date : Fri Jan 29 09:36:12 1993


-- Entity Declaration

ENTITY tsn_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1008;	-- area
    CONSTANT cin_i : NATURAL := 73;	-- cin_i
    CONSTANT tphl_i : NATURAL := 1401;	-- tphl_i
    CONSTANT rdown_i : NATURAL := 1721;	-- rdown_i
    CONSTANT tplh_i : NATURAL := 1879;	-- tplh_i
    CONSTANT rup_i : NATURAL := 2910;	-- rup_i
    CONSTANT cin_v : NATURAL := 64;	-- cin_v
    CONSTANT tphl_v : NATURAL := 674;	-- tphl_v
    CONSTANT rdown_v : NATURAL := 1721;	-- rdown_v
    CONSTANT tphh_v : NATURAL := 1655;	-- tphh_v
    CONSTANT rup_v : NATURAL := 2910	-- rup_v
  );
  PORT (
  i : in BIT;	-- i
  v : in BIT;	-- v
  f : out MUX_BIT BUS;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END tsn_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF tsn_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on tsn_y"
    SEVERITY WARNING;

	label0 : BLOCK (v = '1')
	BEGIN
	f <= GUARDED not (i);
	END BLOCK label0;
END;