-- VHDL data flow description generated from `ts_y`
--		date : Fri Jan 29 09:34:37 1993


-- Entity Declaration

ENTITY ts_y IS
  GENERIC (
    CONSTANT area : NATURAL := 2016;	-- area
    CONSTANT cin_i : NATURAL := 46;	-- cin_i
    CONSTANT tpll_i : NATURAL := 3062;	-- tpll_i
    CONSTANT rdown_i : NATURAL := 522;	-- rdown_i
    CONSTANT tphh_i : NATURAL := 2927;	-- tphh_i
    CONSTANT rup_i : NATURAL := 798;	-- rup_i
    CONSTANT cin_v : NATURAL := 88;	-- cin_v
    CONSTANT tphl_v : NATURAL := 2507;	-- tphl_v
    CONSTANT rdown_v : NATURAL := 522;	-- rdown_v
    CONSTANT tphh_v : NATURAL := 2626;	-- tphh_v
    CONSTANT rup_v : NATURAL := 798	-- rup_v
  );
  PORT (
  i : in BIT;	-- i
  v : in BIT;	-- v
  t : out MUX_BIT BUS;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END ts_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF ts_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on ts_y"
    SEVERITY WARNING;

	label0 : BLOCK (v = '1')
	BEGIN
	t <= GUARDED i;
	END BLOCK label0;
END;