-- VHDL data flow description generated from `tie_y`
--		date : Fri Jan 22 09:31:28 1993


-- Entity Declaration

ENTITY tie_y IS
  GENERIC (
    CONSTANT area : NATURAL := 252	-- area
  );
  PORT (
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END tie_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF tie_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on tie_y"
    SEVERITY WARNING;

END;