-- VHDL data flow description generated from `sum_y`
--		date : Fri Jan 22 09:30:23 1993


-- Entity Declaration

ENTITY sum_y IS
  GENERIC (
    CONSTANT area : NATURAL := 2016;	-- area
    CONSTANT cin_c0b : NATURAL := 46;	-- cin_c0b
    CONSTANT tphl_c0b : NATURAL := 1075;	-- tphl_c0b
    CONSTANT rdown_c0b : NATURAL := 2582;	-- rdown_c0b
    CONSTANT tplh_c0b : NATURAL := 2057;	-- tplh_c0b
    CONSTANT rup_c0b : NATURAL := 5150;	-- rup_c0b
    CONSTANT cin_ci : NATURAL := 90;	-- cin_ci
    CONSTANT tphl_ci : NATURAL := 4235;	-- tphl_ci
    CONSTANT rdown_ci : NATURAL := 3540;	-- rdown_ci
    CONSTANT tplh_ci : NATURAL := 5791;	-- tplh_ci
    CONSTANT rup_ci : NATURAL := 7291;	-- rup_ci
    CONSTANT cin_si : NATURAL := 89;	-- cin_si
    CONSTANT tphl_si : NATURAL := 5113;	-- tphl_si
    CONSTANT rdown_si : NATURAL := 3540;	-- rdown_si
    CONSTANT tplh_si : NATURAL := 6761;	-- tplh_si
    CONSTANT rup_si : NATURAL := 7291;	-- rup_si
    CONSTANT cin_pi : NATURAL := 91;	-- cin_pi
    CONSTANT tphl_pi : NATURAL := 3277;	-- tphl_pi
    CONSTANT rdown_pi : NATURAL := 3540;	-- rdown_pi
    CONSTANT tplh_pi : NATURAL := 4120;	-- tplh_pi
    CONSTANT rup_pi : NATURAL := 7291	-- rup_pi
  );
  PORT (
  pi : in BIT;	-- pi
  ci : in BIT;	-- ci
  si : in BIT;	-- si
  c0b : in BIT;	-- c0b
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END sum_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF sum_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on sum_y"
    SEVERITY WARNING;


f <= not ((((si and pi) and ci) or (c0b and ((si or pi) or ci))));
END;