-- VHDL data flow description generated from `p1_y`
--		date : Fri Jan 22 09:28:08 1993


-- Entity Declaration

ENTITY p1_y IS
  GENERIC (
    CONSTANT area : NATURAL := 756;	-- area
    CONSTANT cin_i : NATURAL := 40;	-- cin_i
    CONSTANT tpll_i : NATURAL := 1479;	-- tpll_i
    CONSTANT rdown_i : NATURAL := 1044;	-- rdown_i
    CONSTANT tphh_i : NATURAL := 1387;	-- tphh_i
    CONSTANT rup_i : NATURAL := 1596	-- rup_i
  );
  PORT (
  i : in BIT;	-- i
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END p1_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF p1_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on p1_y"
    SEVERITY WARNING;


t <= i;
END;