-- VHDL data flow description generated from `op3_y`
--		date : Fri Jan 22 09:27:01 1993


-- Entity Declaration

ENTITY op3_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1512;	-- area
    CONSTANT cin_i0 : NATURAL := 62;	-- cin_i0
    CONSTANT tpll_i0 : NATURAL := 4346;	-- tpll_i0
    CONSTANT rdown_i0 : NATURAL := 1044;	-- rdown_i0
    CONSTANT tphh_i0 : NATURAL := 3476;	-- tphh_i0
    CONSTANT rup_i0 : NATURAL := 1596;	-- rup_i0
    CONSTANT cin_i1 : NATURAL := 62;	-- cin_i1
    CONSTANT tpll_i1 : NATURAL := 3857;	-- tpll_i1
    CONSTANT rdown_i1 : NATURAL := 1044;	-- rdown_i1
    CONSTANT tphh_i1 : NATURAL := 2685;	-- tphh_i1
    CONSTANT rup_i1 : NATURAL := 1596;	-- rup_i1
    CONSTANT cin_i2 : NATURAL := 62;	-- cin_i2
    CONSTANT tpll_i2 : NATURAL := 2679;	-- tpll_i2
    CONSTANT rdown_i2 : NATURAL := 1044;	-- rdown_i2
    CONSTANT tphh_i2 : NATURAL := 1869;	-- tphh_i2
    CONSTANT rup_i2 : NATURAL := 1596	-- rup_i2
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END op3_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF op3_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on op3_y"
    SEVERITY WARNING;


t <= ((i0 or i1) or i2);
END;