-- VHDL data flow description generated from `op2_y`
--		date : Fri Jan 22 09:25:52 1993


-- Entity Declaration

ENTITY op2_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1260;	-- area
    CONSTANT cin_i0 : NATURAL := 62;	-- cin_i0
    CONSTANT tpll_i0 : NATURAL := 2425;	-- tpll_i0
    CONSTANT rdown_i0 : NATURAL := 1044;	-- rdown_i0
    CONSTANT tphh_i0 : NATURAL := 2620;	-- tphh_i0
    CONSTANT rup_i0 : NATURAL := 1596;	-- rup_i0
    CONSTANT cin_i1 : NATURAL := 62;	-- cin_i1
    CONSTANT tpll_i1 : NATURAL := 1975;	-- tpll_i1
    CONSTANT rdown_i1 : NATURAL := 1044;	-- rdown_i1
    CONSTANT tphh_i1 : NATURAL := 1801;	-- tphh_i1
    CONSTANT rup_i1 : NATURAL := 1596	-- rup_i1
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END op2_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF op2_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on op2_y"
    SEVERITY WARNING;


t <= (i0 or i1);
END;