-- VHDL data flow description generated from `one_y`
--		date : Fri Jan 22 09:24:46 1993


-- Entity Declaration

ENTITY one_y IS
  GENERIC (
    CONSTANT area : NATURAL := 504;	-- area
    CONSTANT rup : NATURAL := 4020	-- rup
  );
  PORT (
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END one_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF one_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on one_y"
    SEVERITY WARNING;


t <= '1';
END;