-- VHDL data flow description generated from `no3_y`
--		date : Fri Jan 22 09:14:33 1993


-- Entity Declaration

ENTITY no3_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1260;	-- area
    CONSTANT cin_i2 : NATURAL := 62;	-- cin_i2
    CONSTANT tphl_i2 : NATURAL := 2479;	-- tphl_i2
    CONSTANT rdown_i2 : NATURAL := 2089;	-- rdown_i2
    CONSTANT tplh_i2 : NATURAL := 3344;	-- tplh_i2
    CONSTANT rup_i2 : NATURAL := 4121;	-- rup_i2
    CONSTANT cin_i1 : NATURAL := 62;	-- cin_i1
    CONSTANT tphl_i1 : NATURAL := 1687;	-- tphl_i1
    CONSTANT rdown_i1 : NATURAL := 2089;	-- rdown_i1
    CONSTANT tplh_i1 : NATURAL := 2856;	-- tplh_i1
    CONSTANT rup_i1 : NATURAL := 4121;	-- rup_i1
    CONSTANT cin_i0 : NATURAL := 62;	-- cin_i0
    CONSTANT tphl_i0 : NATURAL := 857;	-- tphl_i0
    CONSTANT rdown_i0 : NATURAL := 2089;	-- rdown_i0
    CONSTANT tplh_i0 : NATURAL := 1676;	-- tplh_i0
    CONSTANT rup_i0 : NATURAL := 4121	-- rup_i0
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END no3_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF no3_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on no3_y"
    SEVERITY WARNING;


f <= not (((i0 or i1) or i2));
END;