-- VHDL data flow description generated from `nmx2_y`
--		date : Fri Jan 22 09:12:21 1993


-- Entity Declaration

ENTITY nmx2_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1512;	-- area
    CONSTANT cin_i1 : NATURAL := 73;	-- cin_i1
    CONSTANT tphl_i1 : NATURAL := 1118;	-- tphl_i1
    CONSTANT rdown_i1 : NATURAL := 1721;	-- rdown_i1
    CONSTANT tplh_i1 : NATURAL := 2210;	-- tplh_i1
    CONSTANT rup_i1 : NATURAL := 2910;	-- rup_i1
    CONSTANT cin_j1 : NATURAL := 73;	-- cin_j1
    CONSTANT tphl_j1 : NATURAL := 2566;	-- tphl_j1
    CONSTANT rdown_j1 : NATURAL := 1721;	-- rdown_j1
    CONSTANT tplh_j1 : NATURAL := 3264;	-- tplh_j1
    CONSTANT rup_j1 : NATURAL := 2910;	-- rup_j1
    CONSTANT cin_j0 : NATURAL := 73;	-- cin_j0
    CONSTANT tphl_j0 : NATURAL := 2632;	-- tphl_j0
    CONSTANT rdown_j0 : NATURAL := 1721;	-- rdown_j0
    CONSTANT tplh_j0 : NATURAL := 3008;	-- tplh_j0
    CONSTANT rup_j0 : NATURAL := 2910;	-- rup_j0
    CONSTANT cin_i0 : NATURAL := 73;	-- cin_i0
    CONSTANT tphl_i0 : NATURAL := 1173;	-- tphl_i0
    CONSTANT rdown_i0 : NATURAL := 1721;	-- rdown_i0
    CONSTANT tplh_i0 : NATURAL := 1953;	-- tplh_i0
    CONSTANT rup_i0 : NATURAL := 2910	-- rup_i0
  );
  PORT (
  j0 : in BIT;	-- j0
  j1 : in BIT;	-- j1
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END nmx2_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF nmx2_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on nmx2_y"
    SEVERITY WARNING;


f <= ((j0 and j1) nor (i0 and i1));
END;