-- VHDL data flow description generated from `nao4_y`
--		date : Fri Jan 22 09:10:08 1993


-- Entity Declaration

ENTITY nao4_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1512;	-- area
    CONSTANT cin_i : NATURAL := 62;	-- cin_i
    CONSTANT tphl_i : NATURAL := 871;	-- tphl_i
    CONSTANT rdown_i : NATURAL := 2089;	-- rdown_i
    CONSTANT tplh_i : NATURAL := 1226;	-- tplh_i
    CONSTANT rup_i : NATURAL := 2910;	-- rup_i
    CONSTANT cin_j0 : NATURAL := 78;	-- cin_j0
    CONSTANT tphl_j0 : NATURAL := 2568;	-- tphl_j0
    CONSTANT rdown_j0 : NATURAL := 1888;	-- rdown_j0
    CONSTANT tplh_j0 : NATURAL := 2352;	-- tplh_j0
    CONSTANT rup_j0 : NATURAL := 2910;	-- rup_j0
    CONSTANT cin_j1 : NATURAL := 78;	-- cin_j1
    CONSTANT tphl_j1 : NATURAL := 2619;	-- tphl_j1
    CONSTANT rdown_j1 : NATURAL := 1888;	-- rdown_j1
    CONSTANT tplh_j1 : NATURAL := 2673;	-- tplh_j1
    CONSTANT rup_j1 : NATURAL := 2910;	-- rup_j1
    CONSTANT cin_j2 : NATURAL := 78;	-- cin_j2
    CONSTANT tphl_j2 : NATURAL := 2594;	-- tphl_j2
    CONSTANT rdown_j2 : NATURAL := 1888;	-- rdown_j2
    CONSTANT tplh_j2 : NATURAL := 2994;	-- tplh_j2
    CONSTANT rup_j2 : NATURAL := 2910	-- rup_j2
  );
  PORT (
  i : in BIT;	-- i
  j0 : in BIT;	-- j0
  j1 : in BIT;	-- j1
  j2 : in BIT;	-- j2
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END nao4_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF nao4_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on nao4_y"
    SEVERITY WARNING;


f <= (((j0 and j1) and j2) nor i);
END;