-- VHDL data flow description generated from `na3p_y`
--		date : Fri Jan 22 09:06:47 1993


-- Entity Declaration

ENTITY na3p_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1260;	-- area
    CONSTANT cin_i2 : NATURAL := 93;	-- cin_i2
    CONSTANT tphl_i2 : NATURAL := 1235;	-- tphl_i2
    CONSTANT rdown_i2 : NATURAL := 1231;	-- rdown_i2
    CONSTANT tplh_i2 : NATURAL := 1956;	-- tplh_i2
    CONSTANT rup_i2 : NATURAL := 1596;	-- rup_i2
    CONSTANT cin_i1 : NATURAL := 93;	-- cin_i1
    CONSTANT tphl_i1 : NATURAL := 1260;	-- tphl_i1
    CONSTANT rdown_i1 : NATURAL := 1231;	-- rdown_i1
    CONSTANT tplh_i1 : NATURAL := 1724;	-- tplh_i1
    CONSTANT rup_i1 : NATURAL := 1596;	-- rup_i1
    CONSTANT cin_i0 : NATURAL := 93;	-- cin_i0
    CONSTANT tphl_i0 : NATURAL := 1204;	-- tphl_i0
    CONSTANT rdown_i0 : NATURAL := 1231;	-- rdown_i0
    CONSTANT tplh_i0 : NATURAL := 1489;	-- tplh_i0
    CONSTANT rup_i0 : NATURAL := 1596	-- rup_i0
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END na3p_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF na3p_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on na3p_y"
    SEVERITY WARNING;


f <= not (((i2 and i1) and i0));
END;