-- VHDL data flow description generated from `na3_y`
--		date : Fri Jan 22 09:05:43 1993


-- Entity Declaration

ENTITY na3_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1008;	-- area
    CONSTANT cin_i2 : NATURAL := 51;	-- cin_i2
    CONSTANT tphl_i2 : NATURAL := 1258;	-- tphl_i2
    CONSTANT rdown_i2 : NATURAL := 2360;	-- rdown_i2
    CONSTANT tplh_i2 : NATURAL := 1983;	-- tplh_i2
    CONSTANT rup_i2 : NATURAL := 3060;	-- rup_i2
    CONSTANT cin_i1 : NATURAL := 51;	-- cin_i1
    CONSTANT tphl_i1 : NATURAL := 1282;	-- tphl_i1
    CONSTANT rdown_i1 : NATURAL := 2360;	-- rdown_i1
    CONSTANT tplh_i1 : NATURAL := 1748;	-- tplh_i1
    CONSTANT rup_i1 : NATURAL := 3060;	-- rup_i1
    CONSTANT cin_i0 : NATURAL := 51;	-- cin_i0
    CONSTANT tphl_i0 : NATURAL := 1225;	-- tphl_i0
    CONSTANT rdown_i0 : NATURAL := 2360;	-- rdown_i0
    CONSTANT tplh_i0 : NATURAL := 1511;	-- tplh_i0
    CONSTANT rup_i0 : NATURAL := 3060	-- rup_i0
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END na3_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF na3_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on na3_y"
    SEVERITY WARNING;


f <= not (((i2 and i1) and i0));
END;