-- VHDL data flow description generated from `n1_y`
--		date : Fri Jan 22 09:02:16 1993


-- Entity Declaration

ENTITY n1_y IS
  GENERIC (
    CONSTANT area : NATURAL := 504;	-- area
    CONSTANT cin_i : NATURAL := 40;	-- cin_i
    CONSTANT tphl_i : NATURAL := 501;	-- tphl_i
    CONSTANT rdown_i : NATURAL := 2089;	-- rdown_i
    CONSTANT tplh_i : NATURAL := 734;	-- tplh_i
    CONSTANT rup_i : NATURAL := 3060	-- rup_i
  );
  PORT (
  i : in BIT;	-- i
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END n1_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF n1_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on n1_y"
    SEVERITY WARNING;


f <= not (i);
END;