-- VHDL data flow description generated from `mx2_y`
--		date : Fri Jan 22 08:58:53 1993


-- Entity Declaration

ENTITY mx2_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1764;	-- area
    CONSTANT cin_l1 : NATURAL := 40;	-- cin_l1
    CONSTANT tpll_l1 : NATURAL := 2885;	-- tpll_l1
    CONSTANT rdown_l1 : NATURAL := 2089;	-- rdown_l1
    CONSTANT tphh_l1 : NATURAL := 2458;	-- tphh_l1
    CONSTANT rup_l1 : NATURAL := 3060;	-- rup_l1
    CONSTANT cin_i1 : NATURAL := 40;	-- cin_i1
    CONSTANT tpll_i1 : NATURAL := 3138;	-- tpll_i1
    CONSTANT rdown_i1 : NATURAL := 2089;	-- rdown_i1
    CONSTANT tphh_i1 : NATURAL := 2401;	-- tphh_i1
    CONSTANT rup_i1 : NATURAL := 3060;	-- rup_i1
    CONSTANT cin_l0 : NATURAL := 40;	-- cin_l0
    CONSTANT tpll_l0 : NATURAL := 3951;	-- tpll_l0
    CONSTANT rdown_l0 : NATURAL := 2089;	-- rdown_l0
    CONSTANT tphh_l0 : NATURAL := 3988;	-- tphh_l0
    CONSTANT rup_l0 : NATURAL := 3060;	-- rup_l0
    CONSTANT cin_i0 : NATURAL := 40;	-- cin_i0
    CONSTANT tpll_i0 : NATURAL := 4203;	-- tpll_i0
    CONSTANT rdown_i0 : NATURAL := 2089;	-- rdown_i0
    CONSTANT tphh_i0 : NATURAL := 3923;	-- tphh_i0
    CONSTANT rup_i0 : NATURAL := 3060	-- rup_i0
  );
  PORT (
  i0 : in BIT;	-- i0
  l0 : in BIT;	-- l0
  i1 : in BIT;	-- i1
  l1 : in BIT;	-- l1
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END mx2_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF mx2_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on mx2_y"
    SEVERITY WARNING;


t <= ((i1 and l1) or (i0 and l0));
END;