-- VHDL data flow description generated from `ms_y`
--		date : Fri Jan 22 08:56:33 1993


-- Entity Declaration

ENTITY ms_y IS
  GENERIC (
    CONSTANT area : NATURAL := 3024;	-- area
    CONSTANT rup : NATURAL := 1596;	-- rup
    CONSTANT rdown : NATURAL := 2138;	-- rdown
    CONSTANT cin_i : NATURAL := 40;	-- cin_i
    CONSTANT cin_l : NATURAL := 71	-- cin_l
  );
  PORT (
  i : in BIT;	-- i
  l : in BIT;	-- l
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END ms_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF ms_y IS
  SIGNAL dff_s : REG_BIT REGISTER;	-- dff_s

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on ms_y"
    SEVERITY WARNING;

  label0 : BLOCK (l = '0' AND NOT l'stable)
  BEGIN
    dff_s <= GUARDED not (i);
  END BLOCK label0;

t <= not (dff_s);
END;