-- VHDL data flow description generated from `l6r_y`
--		date : Wed Feb 10 12:49:12 1993


-- Entity Declaration

ENTITY l6r_y IS
  GENERIC (
    CONSTANT area : NATURAL := 3276;	-- area
    CONSTANT rup : NATURAL := 3060;	-- rup
    CONSTANT rdown : NATURAL := 2089;	-- rdown
    CONSTANT cin_i0 : NATURAL := 23;	-- cin_i0
    CONSTANT cin_l0 : NATURAL := 16;	-- cin_l0
    CONSTANT cin_i1 : NATURAL := 23;	-- cin_i1
    CONSTANT cin_l1 : NATURAL := 16;	-- cin_l1
    CONSTANT cin_i2 : NATURAL := 23;	-- cin_i2
    CONSTANT cin_l2 : NATURAL := 16;	-- cin_l2
    CONSTANT cin_i3 : NATURAL := 23;	-- cin_i3
    CONSTANT cin_l3 : NATURAL := 16;	-- cin_l3
    CONSTANT cin_i4 : NATURAL := 23;	-- cin_i4
    CONSTANT cin_l4 : NATURAL := 16;	-- cin_l4
    CONSTANT cin_l5 : NATURAL := 15	-- cin_l5
  );
  PORT (
  i0 : in BIT;	-- i0
  l0 : in BIT;	-- l0
  i1 : in BIT;	-- i1
  l1 : in BIT;	-- l1
  i2 : in BIT;	-- i2
  l2 : in BIT;	-- l2
  i3 : in BIT;	-- i3
  l3 : in BIT;	-- l3
  i4 : in BIT;	-- i4
  l4 : in BIT;	-- l4
  l5 : in BIT;	-- l5
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END l6r_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF l6r_y IS
  SIGNAL mpx_s : REG_BIT REGISTER;	-- mpx_s

BEGIN
  ASSERT (not ((((((((((((((((l0 and l1) or (l0 and l2)) or (l1 and l2))
or (l0 and l3)) or (l1 and l3)) or (l2 and l3)) or (l0 and l4))
or (l1 and l4)) or (l2 and l4)) or (l3 and l4)) or (l0 and l5))
or (l1 and l5)) or (l2 and l5)) or (l3 and l5)) or (l4 and l5))) = '1')
    REPORT "conflict when writing into a l6r_y"
    SEVERITY ERROR;

  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on l6r_y"
    SEVERITY WARNING;

  label0 : BLOCK (l0 = '1')
  BEGIN
    mpx_s <= GUARDED i0;
  END BLOCK label0;
  label1 : BLOCK (l1 = '1')
  BEGIN
    mpx_s <= GUARDED i1;
  END BLOCK label1;
  label2 : BLOCK (l2 = '1')
  BEGIN
    mpx_s <= GUARDED i2;
  END BLOCK label2;
  label3 : BLOCK (l3 = '1')
  BEGIN
    mpx_s <= GUARDED i3;
  END BLOCK label3;
  label4 : BLOCK (l4 = '1')
  BEGIN
    mpx_s <= GUARDED i4;
  END BLOCK label4;
  label5 : BLOCK (l5 = '1')
  BEGIN
    mpx_s <= GUARDED '0';
  END BLOCK label5;

t <= mpx_s;
END;