-- VHDL data flow description generated from `l3r_y`
--		date : Wed Feb 10 12:40:05 1993


-- Entity Declaration

ENTITY l3r_y IS
  GENERIC (
    CONSTANT area : NATURAL := 2016;	-- area
    CONSTANT rup : NATURAL := 3060;	-- rup
    CONSTANT rdown : NATURAL := 2089;	-- rdown
    CONSTANT cin_i0 : NATURAL := 23;	-- cin_i0
    CONSTANT cin_l0 : NATURAL := 16;	-- cin_l0
    CONSTANT cin_i1 : NATURAL := 23;	-- cin_i1
    CONSTANT cin_l1 : NATURAL := 16;	-- cin_l1
    CONSTANT cin_l2 : NATURAL := 16	-- cin_l2
  );
  PORT (
  i0 : in BIT;	-- i0
  l0 : in BIT;	-- l0
  i1 : in BIT;	-- i1
  l1 : in BIT;	-- l1
  l2 : in BIT;	-- l2
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END l3r_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF l3r_y IS
  SIGNAL mpx_s : REG_BIT REGISTER;	-- mpx_s

BEGIN
  ASSERT (not ((((l0 and l1) or (l0 and l2)) or (l1 and l2))) = '1')
    REPORT "conflict when writing into a l3r_y"
    SEVERITY ERROR;

  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on l3r_y"
    SEVERITY WARNING;

  label0 : BLOCK (l0 = '1')
  BEGIN
    mpx_s <= GUARDED i0;
  END BLOCK label0;
  label1 : BLOCK (l1 = '1')
  BEGIN
    mpx_s <= GUARDED i1;
  END BLOCK label1;
  label2 : BLOCK (l2 = '1')
  BEGIN
    mpx_s <= GUARDED '0';
  END BLOCK label2;

t <= mpx_s;
END;