-- VHDL data flow description generated from `l1_y`
--		date : Thu Jan 21 18:57:14 1993


-- Entity Declaration

ENTITY l1_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1260;	-- area
    CONSTANT rup : NATURAL := 1596;	-- rup
    CONSTANT rdown : NATURAL := 1044;	-- rdown
    CONSTANT cin_i : NATURAL := 23;	-- cin_i
    CONSTANT cin_l : NATURAL := 16	-- cin_l
  );
  PORT (
  i : in BIT;	-- i
  l : in BIT;	-- l
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END l1_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF l1_y IS
  SIGNAL mpx_s : REG_BIT REGISTER;	-- mpx_s

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on l1_y"
    SEVERITY WARNING;

  label0 : BLOCK (l = '1')
  BEGIN
    mpx_s <= GUARDED i;
  END BLOCK label0;

t <= mpx_s;
END;