-- ###----------------------------------------------------------------### -- # -- file : dlxm_dpt.vbe # -- date : Dec 4 1992 # -- version : m0.3 # -- description : VHDL description of the DLX's data-path (micro- # -- programmed implementation) # -- # -- ###----------------------------------------------------------------### -- -- le chemin de test n'est pas implemente, seuls figurent les connecteurs -- associes scin fonc . -- Dans la simulation fonc doit etre mis a 1 , scin, doivent etre -- mis a zero . entity dlxm_dpt is port( m_ins : in bit_vector (27 downto 7); -- micro-instruction ck : in bit; -- external clock gel : in bit; -- hardware freeze data : inout mux_vector (31 downto 0) bus; -- data bus statin : in bit_vector (31 downto 0); -- lecture registre status statout : out bit_vector (31 downto 0); -- pour modifier registre status ovr : out bit; -- arithm. overflow nul : out bit; -- result = 0 ipc : out bit; -- pc < ill address ir16 : out bit; -- ir(16) vers controle codop : out bit_vector (5 downto 0); -- ir(31:26) vers controle et st adrout : out bit_vector (31 downto 0); -- address bus adr01 : out bit_vector (1 downto 0); -- bits poids faible vers status adr31 : out bit; -- bit poids fort vers status scin : in bit; -- scan in fonc : in bit; -- fonct. mode vdd : in bit; vss : in bit); end dlxm_dpt ; architecture FONCTIONAL of dlxm_dpt is signal ir : reg_vector (31 downto 0) register ; -- instruction reg. constant r0 : bit_vector (31 downto 0) :=X"00000000"; -- general reg #0 = 0 signal r1 : reg_vector (31 downto 0) register ; -- general reg #1 signal r2 : reg_vector (31 downto 0) register ; -- general reg #2 signal r3 : reg_vector (31 downto 0) register ; -- general reg #3 signal r4 : reg_vector (31 downto 0) register ; -- general reg #4 signal r5 : reg_vector (31 downto 0) register ; -- general reg #5 signal r6 : reg_vector (31 downto 0) register ; -- general reg #6 signal r7 : reg_vector (31 downto 0) register ; -- general reg #7 signal r8 : reg_vector (31 downto 0) register ; -- general reg #8 signal r9 : reg_vector (31 downto 0) register ; -- general reg #9 signal r10 : reg_vector (31 downto 0) register ; -- general reg #10 signal r11 : reg_vector (31 downto 0) register ; -- general reg #11 signal r12 : reg_vector (31 downto 0) register ; -- general reg #12 signal r13 : reg_vector (31 downto 0) register ; -- general reg #13 signal r14 : reg_vector (31 downto 0) register ; -- general reg #14 signal r15 : reg_vector (31 downto 0) register ; -- general reg #15 signal r16 : reg_vector (31 downto 0) register ; -- general reg #16 signal r17 : reg_vector (31 downto 0) register ; -- general reg #17 signal r18 : reg_vector (31 downto 0) register ; -- general reg #18 signal r19 : reg_vector (31 downto 0) register ; -- general reg #19 signal r20 : reg_vector (31 downto 0) register ; -- general reg #20 signal r21 : reg_vector (31 downto 0) register ; -- general reg #21 signal r22 : reg_vector (31 downto 0) register ; -- general reg #22 signal r23 : reg_vector (31 downto 0) register ; -- general reg #23 signal r24 : reg_vector (31 downto 0) register ; -- general reg #24 signal r25 : reg_vector (31 downto 0) register ; -- general reg #25 signal r26 : reg_vector (31 downto 0) register ; -- general reg #26 signal r27 : reg_vector (31 downto 0) register ; -- general reg #27 signal r28 : reg_vector (31 downto 0) register ; -- general reg #28 signal r29 : reg_vector (31 downto 0) register ; -- general reg #29 signal r30 : reg_vector (31 downto 0) register ; -- general reg #30 signal r31 : reg_vector (31 downto 0) register ; -- general reg #31 signal pc : reg_vector (31 downto 0) register ; -- progr. counter signal ad : reg_vector (31 downto 0) register ; signal iar : reg_vector (31 downto 0) register ; -- inst. address signal dt : reg_vector (31 downto 0) register ; signal x : bit_vector (31 downto 0) ; -- x operand signal y : bit_vector (31 downto 0) ; -- y operand signal arith_operx : bit_vector (31 downto 0) ; -- x op. for arith. signal arith_opery : bit_vector (31 downto 0) ; -- y op. for arith. signal arith_reslt : bit_vector (31 downto 0) ; -- arith. result signal arith_carry : bit_vector (32 downto 0) ; -- adder's carry signal seq : bit ; -- x = y arith. signal sne : bit ; -- x /= y arith. signal sge : bit ; -- x >= y arith. signal sgt : bit ; -- x > y arith. signal sle : bit ; -- x <= y arith. signal slt : bit ; -- x < y arith. signal shift_in : bit_vector (31 downto 0) ; -- shift right in signal shift_right : bit_vector (31 downto 0) ; -- shift right result signal shift_left : bit_vector (31 downto 0) ; -- shift left result signal wen_reg : bit_vector (31 downto 0) ; -- reg. write enables signal writ_pointer : bit_vector (4 downto 0) ; -- reg. bank write add. signal rs : bit_vector (31 downto 0) ; -- value read from reg. signal rt : bit_vector (31 downto 0) ; -- value read from reg. signal i16,i18,i28 : bit_vector(31 downto 0) ; signal res : bit_vector(31 downto 0) ; constant c0 : bit_vector (31 downto 0) := X"00000000"; constant c1 : bit_vector (31 downto 0) := X"00000001"; constant c4 : bit_vector (31 downto 0) := X"00000004"; constant c16 : bit_vector (31 downto 0) := X"00000010"; constant cb : bit_vector (31 downto 0) := X"000000ff"; constant ch : bit_vector (31 downto 0) := X"0000ffff"; constant x_rs : bit_vector (3 downto 0) := B"0000" ; constant x_rt : bit_vector (3 downto 0) := B"0001" ; constant x_pc : bit_vector (3 downto 0) := B"0100" ; constant x_ad : bit_vector (3 downto 0) := B"0101" ; constant x_sr : bit_vector (3 downto 0) := B"0110" ; constant x_iar : bit_vector (3 downto 0) := B"0111" ; constant x_c0 : bit_vector (3 downto 0) := B"1000" ; constant x_cb : bit_vector (3 downto 0) := B"1100" ; constant x_ch : bit_vector (3 downto 0) := B"1111" ; constant y_i16 : bit_vector (2 downto 0) := B"000" ; constant y_i18 : bit_vector (2 downto 0) := B"001" ; constant y_i28 : bit_vector (2 downto 0) := B"010" ; constant y_dt : bit_vector (2 downto 0) := B"011" ; constant y_ad : bit_vector (2 downto 0) := B"100" ; constant y_c0 : bit_vector (2 downto 0) := B"101" ; constant y_c4 : bit_vector (2 downto 0) := B"110" ; constant y_c16 : bit_vector (2 downto 0) := B"111" ; constant a_sumxy : bit_vector (3 downto 0) := B"0001" ; constant a_difxy : bit_vector (3 downto 0) := B"0010" ; constant a_and : bit_vector (3 downto 0) := B"0100" ; constant a_or : bit_vector (3 downto 0) := B"0101" ; constant a_xor : bit_vector (3 downto 0) := B"0110" ; constant a_sll : bit_vector (3 downto 0) := B"0111" ; constant a_srl : bit_vector (3 downto 0) := B"1000" ; constant a_sra : bit_vector (3 downto 0) := B"1001" ; constant a_seq : bit_vector (3 downto 0) := B"1010" ; constant a_sne : bit_vector (3 downto 0) := B"1011" ; constant a_sge : bit_vector (3 downto 0) := B"1100" ; constant a_sgt : bit_vector (3 downto 0) := B"1101" ; constant a_sle : bit_vector (3 downto 0) := B"1110" ; constant a_slt : bit_vector (3 downto 0) := B"1111" ; constant a_nop : bit_vector (3 downto 0) := B"0000" ; constant r_no : bit_vector (5 downto 0) := B"000000" ; constant r_pc : bit_vector (5 downto 0) := B"000001" ; constant r_ad : bit_vector (5 downto 0) := B"000010" ; constant r_iar : bit_vector (5 downto 0) := B"000100" ; constant r_r31 : bit_vector (5 downto 0) := B"001000" ; constant r_rd : bit_vector (5 downto 0) := B"010000" ; constant r_sr : bit_vector (5 downto 0) := B"100000" ; begin ---------------------------- -- definition des signaux -- ---------------------------- i16(15 downto 0) <= ir(15 downto 0) ; i16(31 downto 16) <= X"ffff" when ir(15)='1' else X"0000" ; i18(1 downto 0) <= B"00" ; i18(17 downto 2) <= ir(15 downto 0) ; i18(31 downto 18) <= X"fff" & B"11" when ir(15)='1' else X"000" & B"00" ; i28(1 downto 0) <= B"00" ; i28(27 downto 2) <= ir(25 downto 0) ; i28(31 downto 28) <= X"f" when ir(25)='1' else X"0" ; writ_pointer <= ir (15 downto 11) when ir(28)='0' else ir (20 downto 16) ; with ir (25 downto 21) select rs <= r0 when B"00000" , r1 when B"00001" , r2 when B"00010" , r3 when B"00011" , r4 when B"00100" , r5 when B"00101" , r6 when B"00110" , r7 when B"00111" , r8 when B"01000" , r9 when B"01001" , r10 when B"01010" , r11 when B"01011" , r12 when B"01100" , r13 when B"01101" , r14 when B"01110" , r15 when B"01111" , r16 when B"10000" , r17 when B"10001" , r18 when B"10010" , r19 when B"10011" , r20 when B"10100" , r21 when B"10101" , r22 when B"10110" , r23 when B"10111" , r24 when B"11000" , r25 when B"11001" , r26 when B"11010" , r27 when B"11011" , r28 when B"11100" , r29 when B"11101" , r30 when B"11110" , r31 when B"11111" ; with ir (20 downto 16) select rt <= r0 when B"00000" , r1 when B"00001" , r2 when B"00010" , r3 when B"00011" , r4 when B"00100" , r5 when B"00101" , r6 when B"00110" , r7 when B"00111" , r8 when B"01000" , r9 when B"01001" , r10 when B"01010" , r11 when B"01011" , r12 when B"01100" , r13 when B"01101" , r14 when B"01110" , r15 when B"01111" , r16 when B"10000" , r17 when B"10001" , r18 when B"10010" , r19 when B"10011" , r20 when B"10100" , r21 when B"10101" , r22 when B"10110" , r23 when B"10111" , r24 when B"11000" , r25 when B"11001" , r26 when B"11010" , r27 when B"11011" , r28 when B"11100" , r29 when B"11101" , r30 when B"11110" , r31 when B"11111" ; ------------------------------------- -- definition des operandes x et y -- ------------------------------------- with m_ins (27 downto 24) select x <= rs when x_rs , rt when x_rt , pc when x_pc , ad when x_ad , statin when x_sr , iar when x_iar , c0 when x_c0 , cb when x_cb , ch when x_ch , c0 when others ; with m_ins (23 downto 21) select y <= i16 when y_i16 , i18 when y_i18 , i28 when y_i28 , dt when y_dt , ad when y_ad , c0 when y_c0 , c4 when y_c4 , c16 when y_c16 , c0 when others ; -------------------------------- -- definition des operations -- -------------------------------- arith_operx (31 downto 0) <= x ; with m_ins (20 downto 17) select arith_opery (31 downto 0) <= y when a_sumxy , not (y) when others ; with m_ins (20 downto 17) select arith_carry (0) <= '0' when a_sumxy , '1' when others ; arith_carry (32 downto 1) <= (arith_operx and arith_opery ) or (arith_operx and arith_carry (31 downto 0)) or (arith_opery and arith_carry (31 downto 0)) ; arith_reslt (31 downto 0) <= arith_operx xor arith_carry (31 downto 0) xor arith_opery ; -------------------------- -- definition des tests -- -------------------------- seq <= '1' when (arith_reslt = X"00000000") else '0' ; sgt <= '1' when ((x(31) xor y(31) ='0') and (arith_reslt (31) = '0') and (seq = '0')) else '1' when (x(31)='0' and y(31)='1') else '0' ; sne <= not (seq) ; sge <= sgt or seq; slt <= not (sge); sle <= slt or seq; -------------------------- -- definition des flags -- -------------------------- nul <= '1' when (res(31 downto 0) = X"00000000") else '0' ; ovr <= arith_carry (32) xor arith_carry (31) when (ir(31 downto 29)=B"000") else '0' ; ipc <='1'when (m_ins(11)='1' and res (1 downto 0) /= B"00") else '1'when (m_ins(11)='1' and res(31)='1' and statin(0)='1') else '0' ; ---------------------------- -- definition des sorties -- ---------------------------- ir16 <= ir(16) ; codop(5 downto 0) <= ir(31 downto 26) ; write_data : block ((gel='0') and (m_ins(8 downto 7)=B"00")) begin data(31 downto 0) <= guarded res(31 downto 0) ; end block ; statout <= res(31 downto 0) when (m_ins(16)='1') else c0 ; --adrout(31 downto 0) <= pc(31 downto 0) when (m_ins(10)='1' and m_ins(7)='0') else -- ad(31 downto 0) ; adrout(31 downto 0) <= ad(31 downto 0) when (m_ins(10)='0' and m_ins(7)='0') else pc(31 downto 0) ; --adr01(1 downto 0) <= pc(1 downto 0) when (m_ins(10)='1' and m_ins(7)='0') else -- ad(1 downto 0) ; adr01(1 downto 0) <= ad(1 downto 0) when (m_ins(10)='0' and m_ins(7)='0') else pc(1 downto 0) ; --adr31 <= pc(31) when (m_ins(10)='1' and m_ins(7)='0') else -- ad(31) ; adr31 <= ad(31) when (m_ins(10)='0' and m_ins(7)='0') else pc(31) ; ------------------------------- -- chemin de test non implante -- ------------------------------- ------------------------------- -- definition des decalages -- ------------------------------- shift_in <= X"00000000" when m_ins (17) = '0' else -- logical X"ffffffff" when x (31) = '1' else -- arithm. X"00000000" ; -- arithm. with y(4 downto 0) select shift_left <= x (31 downto 0) when B"00000" , x (30 downto 0) & B"0" when B"00001" , x (29 downto 0) & B"00" when B"00010" , x (28 downto 0) & B"000" when B"00011" , x (27 downto 0) & X"0" when B"00100" , x (26 downto 0) & X"0" & B"0" when B"00101" , x (25 downto 0) & X"0" & B"00" when B"00110" , x (24 downto 0) & X"0" & B"000" when B"00111" , x (23 downto 0) & X"00" when B"01000" , x (22 downto 0) & X"00" & B"0" when B"01001" , x (21 downto 0) & X"00" & B"00" when B"01010" , x (20 downto 0) & X"00" & B"000" when B"01011" , x (19 downto 0) & X"000" when B"01100" , x (18 downto 0) & X"000" & B"0" when B"01101" , x (17 downto 0) & X"000" & B"00" when B"01110" , x (16 downto 0) & X"000" & B"000" when B"01111" , x (15 downto 0) & X"0000" when B"10000" , x (14 downto 0) & X"0000" & B"0" when B"10001" , x (13 downto 0) & X"0000" & B"00" when B"10010" , x (12 downto 0) & X"0000" & B"000" when B"10011" , x (11 downto 0) & X"00000" when B"10100" , x (10 downto 0) & X"00000" & B"0" when B"10101" , x (9 downto 0) & X"00000" & B"00" when B"10110" , x (8 downto 0) & X"00000" & B"000" when B"10111" , x (7 downto 0) & X"000000" when B"11000" , x (6 downto 0) & X"000000" & B"0" when B"11001" , x (5 downto 0) & X"000000" & B"00" when B"11010" , x (4 downto 0) & X"000000" & B"000" when B"11011" , x (3 downto 0) & X"0000000" when B"11100" , x (2 downto 0) & X"0000000" & B"0" when B"11101" , x (1 downto 0) & X"0000000" & B"00" when B"11110" , x (0) & X"0000000" & B"000" when B"11111" ; with y(4 downto 0) select shift_right <= x (31 downto 0) when B"00000" , shift_in (0) & x (31 downto 1) when B"00001" , shift_in (0 to 1) & x (31 downto 2) when B"00010" , shift_in (0 to 2) & x (31 downto 3) when B"00011" , shift_in (0 to 3) & x (31 downto 4) when B"00100" , shift_in (0 to 4) & x (31 downto 5) when B"00101" , shift_in (0 to 5) & x (31 downto 6) when B"00110" , shift_in (0 to 6) & x (31 downto 7) when B"00111" , shift_in (0 to 7) & x (31 downto 8) when B"01000" , shift_in (0 to 8) & x (31 downto 9) when B"01001" , shift_in (0 to 9) & x (31 downto 10) when B"01010" , shift_in (0 to 10) & x (31 downto 11) when B"01011" , shift_in (0 to 11) & x (31 downto 12) when B"01100" , shift_in (0 to 12) & x (31 downto 13) when B"01101" , shift_in (0 to 13) & x (31 downto 14) when B"01110" , shift_in (0 to 14) & x (31 downto 15) when B"01111" , shift_in (0 to 15) & x (31 downto 16) when B"10000" , shift_in (0 to 16) & x (31 downto 17) when B"10001" , shift_in (0 to 17) & x (31 downto 18) when B"10010" , shift_in (0 to 18) & x (31 downto 19) when B"10011" , shift_in (0 to 19) & x (31 downto 20) when B"10100" , shift_in (0 to 20) & x (31 downto 21) when B"10101" , shift_in (0 to 21) & x (31 downto 22) when B"10110" , shift_in (0 to 22) & x (31 downto 23) when B"10111" , shift_in (0 to 23) & x (31 downto 24) when B"11000" , shift_in (0 to 24) & x (31 downto 25) when B"11001" , shift_in (0 to 25) & x (31 downto 26) when B"11010" , shift_in (0 to 26) & x (31 downto 27) when B"11011" , shift_in (0 to 27) & x (31 downto 28) when B"11100" , shift_in (0 to 28) & x (31 downto 29) when B"11101" , shift_in (0 to 29) & x (31 downto 30) when B"11110" , shift_in (0 to 30) & x (31) when B"11111" ; ------------------------------------------- -- definition du resultat de l'operation -- ------------------------------------------- with m_ins (20 downto 17) select res <= arith_reslt when a_sumxy , arith_reslt when a_difxy , x and y when a_and , x or y when a_or , x xor y when a_xor , shift_left when a_sll , shift_right when a_srl , shift_right when a_sra , c0 (31 downto 1) & seq when a_seq , c0 (31 downto 1) & sne when a_sne , c0 (31 downto 1) & sge when a_sge , c0 (31 downto 1) & sgt when a_sgt , c0 (31 downto 1) & sle when a_sle , c0 (31 downto 1) & slt when a_slt , c0 when others ; -- a_nop -------------------------------- -- ecriture dans les bascules -- -- "D" sur front descendant -- -------------------------------- write_reg_ext : block (((not ck) and (not gel))='1' and not ck'STABLE) begin with m_ins(10 downto 7) select dt(31 downto 0) <= guarded data(31 downto 0) when B"0010", X"000000" & data(7 downto 0) when B"0110", dt(31 downto 0) when others ; with m_ins(10 downto 7) select ir(31 downto 0) <= guarded data(31 downto 0) when B"1010", ir(31 downto 0) when others ; end block ; with (m_ins (16 downto 11) & writ_pointer (4 downto 0)) select wen_reg <= X"00000001" when B"010000_00000", -- r_rd & B"00000" X"00000002" when B"010000_00001", -- r_rd & B"00001" X"00000004" when B"010000_00010", -- r_rd & B"00010" X"00000008" when B"010000_00011", -- r_rd & B"00011" X"00000010" when B"010000_00100", -- r_rd & B"00100" X"00000020" when B"010000_00101", -- r_rd & B"00101" X"00000040" when B"010000_00110", -- r_rd & B"00110" X"00000080" when B"010000_00111", -- r_rd & B"00111" X"00000100" when B"010000_01000", -- r_rd & B"01000" X"00000200" when B"010000_01001", -- r_rd & B"01001" X"00000400" when B"010000_01010", -- r_rd & B"01010" X"00000800" when B"010000_01011", -- r_rd & B"01011" X"00001000" when B"010000_01100", -- r_rd & B"01100" X"00002000" when B"010000_01101", -- r_rd & B"01101" X"00004000" when B"010000_01110", -- r_rd & B"01110" X"00008000" when B"010000_01111", -- r_rd & B"01111" X"00010000" when B"010000_10000", -- r_rd & B"10000" X"00020000" when B"010000_10001", -- r_rd & B"10001" X"00040000" when B"010000_10010", -- r_rd & B"10010" X"00080000" when B"010000_10011", -- r_rd & B"10011" X"00100000" when B"010000_10100", -- r_rd & B"10100" X"00200000" when B"010000_10101", -- r_rd & B"10101" X"00400000" when B"010000_10110", -- r_rd & B"10110" X"00800000" when B"010000_10111", -- r_rd & B"10111" X"01000000" when B"010000_11000", -- r_rd & B"11000" X"02000000" when B"010000_11001", -- r_rd & B"11001" X"04000000" when B"010000_11010", -- r_rd & B"11010" X"08000000" when B"010000_11011", -- r_rd & B"11011" X"10000000" when B"010000_11100", -- r_rd & B"11100" X"20000000" when B"010000_11101", -- r_rd & B"11101" X"40000000" when B"010000_11110", -- r_rd & B"11110" X"80000000" when B"010000_11111", -- r_rd & B"11111" X"00000000" when others; write_reg : block (((not ck) and (not gel))='1' and not ck'STABLE) begin with m_ins(11) select pc(31 downto 0) <= guarded res(31 downto 0) when '1', pc(31 downto 0) when others ; with m_ins(12) select ad(31 downto 0) <= guarded res(31 downto 0) when '1', ad(31 downto 0) when others ; with m_ins(13) select iar(31 downto 0) <= guarded res(31 downto 0) when '1', iar(31 downto 0) when others ; end block; write_r1 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (1 ) = '1')) begin r1 <= guarded res; end block; write_r2 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (2 ) = '1')) begin r2 <= guarded res; end block; write_r3 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (3 ) = '1')) begin r3 <= guarded res; end block; write_r4 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (4 ) = '1')) begin r4 <= guarded res; end block; write_r5 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (5 ) = '1')) begin r5 <= guarded res; end block; write_r6 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (6 ) = '1')) begin r6 <= guarded res; end block; write_r7 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (7 ) = '1')) begin r7 <= guarded res; end block; write_r8 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (8 ) = '1')) begin r8 <= guarded res; end block; write_r9 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (9 ) = '1')) begin r9 <= guarded res; end block; write_r10 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (10) = '1')) begin r10 <= guarded res; end block; write_r11 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (11) = '1')) begin r11 <= guarded res; end block; write_r12 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (12) = '1')) begin r12 <= guarded res; end block; write_r13 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (13) = '1')) begin r13 <= guarded res; end block; write_r14 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (14) = '1')) begin r14 <= guarded res; end block; write_r15 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (15) = '1')) begin r15 <= guarded res; end block; write_r16 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (16) = '1')) begin r16 <= guarded res; end block; write_r17 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (17) = '1')) begin r17 <= guarded res; end block; write_r18 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (18) = '1')) begin r18 <= guarded res; end block; write_r19 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (19) = '1')) begin r19 <= guarded res; end block; write_r20 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (20) = '1')) begin r20 <= guarded res; end block; write_r21 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (21) = '1')) begin r21 <= guarded res; end block; write_r22 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (22) = '1')) begin r22 <= guarded res; end block; write_r23 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (23) = '1')) begin r23 <= guarded res; end block; write_r24 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (24) = '1')) begin r24 <= guarded res; end block; write_r25 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (25) = '1')) begin r25 <= guarded res; end block; write_r26 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (26) = '1')) begin r26 <= guarded res; end block; write_r27 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (27) = '1')) begin r27 <= guarded res; end block; write_r28 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (28) = '1')) begin r28 <= guarded res; end block; write_r29 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (29) = '1')) begin r29 <= guarded res; end block; write_r30 : block ((ck = '0') and (not ck'STABLE) and (gel = '0') and (wen_reg (30) = '1')) begin r30 <= guarded res ; end block; write_r31 : block ( (ck = '0') and (not ck'STABLE) and (gel = '0') and ((wen_reg (31) = '1') or (m_ins (16 downto 11) = r_r31))) begin r31 <= guarded res; end block; end FONCTIONAL ;