-- VHDL data flow description generated from `cry_y`
--		date : Thu Jan 21 18:56:08 1993


-- Entity Declaration

ENTITY cry_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1512;	-- area
    CONSTANT cin_ci : NATURAL := 89;	-- cin_ci
    CONSTANT tphl_ci : NATURAL := 2017;	-- tphl_ci
    CONSTANT rdown_ci : NATURAL := 2582;	-- rdown_ci
    CONSTANT tplh_ci : NATURAL := 3345;	-- tplh_ci
    CONSTANT rup_ci : NATURAL := 5150;	-- rup_ci
    CONSTANT cin_pi : NATURAL := 90;	-- cin_pi
    CONSTANT tphl_pi : NATURAL := 2564;	-- tphl_pi
    CONSTANT rdown_pi : NATURAL := 2582;	-- rdown_pi
    CONSTANT tplh_pi : NATURAL := 3656;	-- tplh_pi
    CONSTANT rup_pi : NATURAL := 5150;	-- rup_pi
    CONSTANT cin_si : NATURAL := 46;	-- cin_si
    CONSTANT tphl_si : NATURAL := 1060;	-- tphl_si
    CONSTANT rdown_si : NATURAL := 2582;	-- rdown_si
    CONSTANT tplh_si : NATURAL := 2027;	-- tplh_si
    CONSTANT rup_si : NATURAL := 5150	-- rup_si
  );
  PORT (
  pi : in BIT;	-- pi
  ci : in BIT;	-- ci
  si : in BIT;	-- si
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END cry_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF cry_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on cry_y"
    SEVERITY WARNING;


f <= not (((si and ci) or (pi and (si or ci))));
END;