-- VHDL data flow description generated from `b1_y`
--		date : Thu Jan 21 18:55:03 1993


-- Entity Declaration

ENTITY b1_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1008;	-- area
    CONSTANT cin_i : NATURAL := 51;	-- cin_i
    CONSTANT tpll_i : NATURAL := 1663;	-- tpll_i
    CONSTANT rdown_i : NATURAL := 522;	-- rdown_i
    CONSTANT tphh_i : NATURAL := 1400;	-- tphh_i
    CONSTANT rup_i : NATURAL := 798	-- rup_i
  );
  PORT (
  i : in BIT;	-- i
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END b1_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF b1_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on b1_y"
    SEVERITY WARNING;


t <= i;
END;