-- VHDL data flow description generated from `annup_y`
--		date : Thu Jan 21 18:53:58 1993


-- Entity Declaration

ENTITY annup_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1260;	-- area
    CONSTANT cin_i2 : NATURAL := 42;	-- cin_i2
    CONSTANT tphl_i2 : NATURAL := 1005;	-- tphl_i2
    CONSTANT rdown_i2 : NATURAL := 2582;	-- rdown_i2
    CONSTANT tplh_i2 : NATURAL := 2876;	-- tplh_i2
    CONSTANT rup_i2 : NATURAL := 6086;	-- rup_i2
    CONSTANT cin_i1 : NATURAL := 42;	-- cin_i1
    CONSTANT tphl_i1 : NATURAL := 1528;	-- tphl_i1
    CONSTANT rdown_i1 : NATURAL := 2582;	-- rdown_i1
    CONSTANT tplh_i1 : NATURAL := 3325;	-- tplh_i1
    CONSTANT rup_i1 : NATURAL := 6086;	-- rup_i1
    CONSTANT cin_i4 : NATURAL := 42;	-- cin_i4
    CONSTANT tphl_i4 : NATURAL := 960;	-- tphl_i4
    CONSTANT rdown_i4 : NATURAL := 2582;	-- rdown_i4
    CONSTANT tplh_i4 : NATURAL := 2113;	-- tplh_i4
    CONSTANT rup_i4 : NATURAL := 6086;	-- rup_i4
    CONSTANT cin_i3 : NATURAL := 42;	-- cin_i3
    CONSTANT tphl_i3 : NATURAL := 1499;	-- tphl_i3
    CONSTANT rdown_i3 : NATURAL := 2582;	-- rdown_i3
    CONSTANT tplh_i3 : NATURAL := 2562;	-- tplh_i3
    CONSTANT rup_i3 : NATURAL := 6086	-- rup_i3
  );
  PORT (
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  i4 : in BIT;	-- i4
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END annup_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF annup_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on annup_y"
    SEVERITY WARNING;


f <= ((i2 or i1) nand (i3 or i4));
END;