-- VHDL data flow description generated from `a4p_y`
--		date : Thu Jan 21 18:52:52 1993


-- Entity Declaration

ENTITY a4p_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1764;	-- area
    CONSTANT cin_i3 : NATURAL := 74;	-- cin_i3
    CONSTANT tpll_i3 : NATURAL := 2839;	-- tpll_i3
    CONSTANT rdown_i3 : NATURAL := 1044;	-- rdown_i3
    CONSTANT tphh_i3 : NATURAL := 2467;	-- tphh_i3
    CONSTANT rup_i3 : NATURAL := 1596;	-- rup_i3
    CONSTANT cin_i2 : NATURAL := 72;	-- cin_i2
    CONSTANT tpll_i2 : NATURAL := 3299;	-- tpll_i2
    CONSTANT rdown_i2 : NATURAL := 1044;	-- rdown_i2
    CONSTANT tphh_i2 : NATURAL := 2613;	-- tphh_i2
    CONSTANT rup_i2 : NATURAL := 1596;	-- rup_i2
    CONSTANT cin_i1 : NATURAL := 72;	-- cin_i1
    CONSTANT tpll_i1 : NATURAL := 3759;	-- tpll_i1
    CONSTANT rdown_i1 : NATURAL := 1044;	-- rdown_i1
    CONSTANT tphh_i1 : NATURAL := 2684;	-- tphh_i1
    CONSTANT rup_i1 : NATURAL := 1596;	-- rup_i1
    CONSTANT cin_i0 : NATURAL := 72;	-- cin_i0
    CONSTANT tpll_i0 : NATURAL := 4218;	-- tpll_i0
    CONSTANT rdown_i0 : NATURAL := 1044;	-- rdown_i0
    CONSTANT tphh_i0 : NATURAL := 2678;	-- tphh_i0
    CONSTANT rup_i0 : NATURAL := 1596	-- rup_i0
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END a4p_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF a4p_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on a4p_y"
    SEVERITY WARNING;


t <= (((i0 and i1) and i2) and i3);
END;