-- VHDL data flow description generated from `a4_y`
--		date : Thu Jan 21 18:51:46 1993


-- Entity Declaration

ENTITY a4_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1512;	-- area
    CONSTANT cin_i2 : NATURAL := 39;	-- cin_i2
    CONSTANT tpll_i2 : NATURAL := 2930;	-- tpll_i2
    CONSTANT rdown_i2 : NATURAL := 2089;	-- rdown_i2
    CONSTANT tphh_i2 : NATURAL := 2515;	-- tphh_i2
    CONSTANT rup_i2 : NATURAL := 3060;	-- rup_i2
    CONSTANT cin_i1 : NATURAL := 39;	-- cin_i1
    CONSTANT tpll_i1 : NATURAL := 3396;	-- tpll_i1
    CONSTANT rdown_i1 : NATURAL := 2089;	-- rdown_i1
    CONSTANT tphh_i1 : NATURAL := 2665;	-- tphh_i1
    CONSTANT rup_i1 : NATURAL := 3060;	-- rup_i1
    CONSTANT cin_i0 : NATURAL := 39;	-- cin_i0
    CONSTANT tpll_i0 : NATURAL := 3862;	-- tpll_i0
    CONSTANT rdown_i0 : NATURAL := 2089;	-- rdown_i0
    CONSTANT tphh_i0 : NATURAL := 2736;	-- tphh_i0
    CONSTANT rup_i0 : NATURAL := 3060;	-- rup_i0
    CONSTANT cin_i3 : NATURAL := 39;	-- cin_i3
    CONSTANT tpll_i3 : NATURAL := 4327;	-- tpll_i3
    CONSTANT rdown_i3 : NATURAL := 2089;	-- rdown_i3
    CONSTANT tphh_i3 : NATURAL := 2731;	-- tphh_i3
    CONSTANT rup_i3 : NATURAL := 3060	-- rup_i3
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END a4_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF a4_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on a4_y"
    SEVERITY WARNING;


t <= (((i0 and i1) and i2) and i3);
END;