-- VHDL data flow description generated from `a3_y`
--		date : Thu Jan 21 18:49:36 1993


-- Entity Declaration

ENTITY a3_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1260;	-- area
    CONSTANT cin_i0 : NATURAL := 28;	-- cin_i0
    CONSTANT tpll_i0 : NATURAL := 2863;	-- tpll_i0
    CONSTANT rdown_i0 : NATURAL := 2089;	-- rdown_i0
    CONSTANT tphh_i0 : NATURAL := 2683;	-- tphh_i0
    CONSTANT rup_i0 : NATURAL := 3060;	-- rup_i0
    CONSTANT cin_i1 : NATURAL := 28;	-- cin_i1
    CONSTANT tpll_i1 : NATURAL := 2623;	-- tpll_i1
    CONSTANT rdown_i1 : NATURAL := 2089;	-- rdown_i1
    CONSTANT tphh_i1 : NATURAL := 2708;	-- tphh_i1
    CONSTANT rup_i1 : NATURAL := 3060;	-- rup_i1
    CONSTANT cin_i2 : NATURAL := 28;	-- cin_i2
    CONSTANT tpll_i2 : NATURAL := 2382;	-- tpll_i2
    CONSTANT rdown_i2 : NATURAL := 2089;	-- rdown_i2
    CONSTANT tphh_i2 : NATURAL := 2651;	-- tphh_i2
    CONSTANT rup_i2 : NATURAL := 3060	-- rup_i2
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END a3_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF a3_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on a3_y"
    SEVERITY WARNING;


t <= ((i0 and i1) and i2);
END;