-- VHDL data flow description generated from `a2_y`
--		date : Thu Jan 21 18:47:09 1993


-- Entity Declaration

ENTITY a2_y IS
  GENERIC (
    CONSTANT area : NATURAL := 1008;	-- area
    CONSTANT cin_i0 : NATURAL := 29;	-- cin_i0
    CONSTANT tpll_i0 : NATURAL := 2043;	-- tpll_i0
    CONSTANT rdown_i0 : NATURAL := 2089;	-- rdown_i0
    CONSTANT tphh_i0 : NATURAL := 1776;	-- tphh_i0
    CONSTANT rup_i0 : NATURAL := 3060;	-- rup_i0
    CONSTANT cin_i1 : NATURAL := 28;	-- cin_i1
    CONSTANT tpll_i1 : NATURAL := 2287;	-- tpll_i1
    CONSTANT rdown_i1 : NATURAL := 2089;	-- rdown_i1
    CONSTANT tphh_i1 : NATURAL := 1735;	-- tphh_i1
    CONSTANT rup_i1 : NATURAL := 3060	-- rup_i1
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END a2_y;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF a2_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on a2_y"
    SEVERITY WARNING;


t <= (i0 and i1);
END;