EE 8993 VHDL Modeling Course

This is the home page for VHDL Modeling Course to be taught first summer term '97. I am assuming that everybody is already familiar with some aspects of VHDL via the Digital System Design course (Sam Russ) or my Computer Architecture course. This object of this course is to introduce the student to more of the VHDL modeling language than what has been covered in previous courses.

Textbook, WWW Resources

From the digital design course you should already have a textbook which talks about many of the features of the language. Because of this, I have assigned the IEEE Standard VHDL Language Reference Manual as the textbook for this course. This is not that readable, but it is the definitive reference for the language. There are MANY web-based resources for additional information on the language. Here are references to some of them.

General VHDL Information Sites

• VHDL International User's Forum
• RASSP VHDL Information Site, follow 'Related Links' to get to tutorials (Here)

VHDL Tutorials

• VHDL for Synthesis (B. Reese) (Here)
• VHDL Course developed by Scott Calhoun
• Green Mountain Tutorial (Here)
• Hardware Engineers Guide to VHDL

Verilog Tutorials

• Verilog Intro (Daniel Hyde, Bucknell) Nice tutorial
• Verilog vs VHDL (Douglas J. Smith, Veribest Incorporated) Neutral comparison of the two languages
• Celia's Verilog page General Verilog Information

The Verilog compiler command under Unix is qvlcom, under V-system (Win95/WinNT) it is vlog. Running the simulator for Verilog models is exactly the same as for VHDL.

Policy

The grading policy will be:

• 60% simulations
• 40% Tests (2 tests)

All simulations are to be INDIVIDUAL work. You may discuss the assignments with other students but you may not share any code, or show anybody your code as examples of how to do something. Any violations of this policy will result in the assignment of a failing grade for the ENTIRE course.

The current schedule is:

• May 27-May 30th, Classes Tue-Fri. Sim #1 due May 30th.
• J2 - J6, Classes. Sim #2 due June 4, Test #1 June 5th.
• J9-11 Off (at DAC). J12-J13, Class. Sim #3 due June 13th.
• J16, Off (at Motorola). J17 - J20 Classes
• J23 class. Sim #4 due J23rd. Final either J24 or J25.

Links to Course Information

• Introduction to the Mentor QHDL Environment
• Mentor QHDL Frequently Asked Questions
• Simulation #1 Assignment
• Simulation #2 Assignment
• Simulation #3 Assignment
• Simulation #4 Assignment
• Simulation #5 Assignment