Test Setup
Hspice Models: .inc ‘/ecad/local/cadence/cysrc/t/2.0/hp14tb/models/trtc.cor’ .inc ‘/ecad/local/cadence/cysrc/t/2.0/hp14tb/models/tt.cor’
NMOS, PMOS model names are ‘N’, ‘P’ respectively:
M1 y a vdd vdd P W=1.8U L = 0.6U M2 y a gnd gnd N W=0.9U L=0.6U
Switching point of anywhere between 35% and 65% Vdd is ok. You also need to keep the TPLH and TPHL ratio to under 1.4 (take the larger of the two, divide by the smaller). This makes sure the drive strengths of the PTREE and NTREE are somewhat matched.
Determine switching point of 1X size first, then check 2X and 4X sizes. Widths must be kept a multiple of 0.3U (a multiple of lambda).