Transistor Sizing
a. Use minimum size for NMOS tree, size PMOS to get appropriate DC switching point.
b. Which path in circuit do we want to speed up?
For full adder, we are concerned about the case of CarryIn going from 0 to 1 (Carry propagate case).
Thus we want to speed up Cout TPLH .
Simulate for a NO LOAD condition. We want to find appropriate transistor sizes for improving internal delay. Note that if we just increase the size of all transistors, the delay will remain the same!!! (see previous discussion on no load delay).