Decode/Rename/Reordering/Issue/Dispatch Example

9/28/98


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Table of Contents

Decode/Rename/Reordering/Issue/Dispatch Example

Key Elements - Register File, Shelving Buffers

Key Elements - Reorder Buffer (ROB), ROB Map

Fetch

Decode/Reorder/Rename

Decode/Reorder/Rename (cont)

Instruction A: ROB allocate, Op fetch, Rename, Issue (add r8, r0, #25)

Instruction A: ROB allocate, Op fetch, Rename, Issue (add r8, r0, #25)

Operand Fetch

Instruction A: ROB allocate, Op fetch, Rename, Issue (add r8, r0, #25)

Instruction B: ROB allocate, Op fetch, Rename, Issue add r8, r8, #30

Instruction B: ROB allocate, Op fetch, Rename, Issue add r8, r8, #30

Instruction B: ROB allocate, Op fetch, Rename, Issue add r8, r8, #30

Operands are determined before RENAMING!

Instruction C: ROB shown after allocate, Op fetch, Rename, Issue after add r9, r8, #50

Instruction D: ROB shown after allocate, Op fetch, Rename, Issue of add r10, r9, r8

Comments

Instruction Dispatch by CRS (clock 3)

After Instruction Dispatch by CRS (Clock 3)

Clock 4: Execution of Instruction A

Clock 4: Execution of instruction A (Update of Reorder buffer)

Clock 4: Dispatch

Reality Check

Clock 5: Execution of instruction B

Clock 5: Execution of instruction B (Update of Reorder buffer)

Clock 5: Execution of instruction B (After retirement of instruction A)

Clock 5: Dispatch

ROB Status Changes

Clock 6: Execution of instruction C

Clock 6: Execution of instruction C (Update of Reorder buffer)

Clock 6: Execution of instruction C (Retire Instruction B)

Clock 6: Dispatch

Clock 7: Execution of instruction D

Clock 7: Execution of instruction D (retire instruction c)

Clock 8: Execution of instruction ??? (retire instruction D)

Comments

Controlling Stalls - the CRS

Controlling Stalls -- the DRR

Re-fetching Operands of Rejected Instructions

Re-Fetching operands (cont).

How is operand re-fetching different?

Controlling Stalls - the Execution Units

Determining if ROB is full

Load/Store Shelves versus Mult/Integer shelves

Dispatch Load/Store versus Dispatch of Mult/Int

Instruction Retirement

Register R0

Author: Bob Reese

Email: reese@erc.msstate.edu

Home Page: http://www.erc.msstate.edu/~reese

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