Superscalar Processors

Table of Contents

Superscalar Processors

Examples of Different Implementations of Same ISA

Figure 7.2, 7.3 of Text (pgs. 188, 189)

Tasks of Superscalar Processing

Parallel Decode/Instruction Issue

Predecoding

Instruction Issue

More on Shelving (Figure 7.11)

How many entries in Shelving Buffers ?

Shelving Buffer Entry (Figure 7.38)

Email: reese@erc.msstate.edu

Home Page: http://www.erc.msstate.edu/~reese

Download presentation source