#include "package.defs"

library work;
use work.phase.all;

entity  PL_OR301 is 
generic (
 MGeneration : boolean := FALSE
);

port (
 signal R: in bit_type;          
 signal FI:    in bit_type;
 signal A_V, A_T: in bit_type;
 signal B_V, B_T: in bit_type;
 signal C_V, C_T: in bit_type;
 signal FO,FO_B:       out bit_type;
 signal O_V, O_T: out bit_type );
end PL_OR301;

architecture behavior of PL_OR301 is
begin
process (R, A_V, A_T, B_V, B_T, C_V, C_T, FI) 

variable gate_phase: bit_type := EVEN_PHASE;
variable cycle_number: integer := 0;

 begin

   if (R = '1') then
     gate_phase := EVEN_PHASE;
     O_V <= '1' after PHASE_DELAY;
     O_T <= lookup_phase('1',not(EVEN_PHASE)) after PHASE_DELAY;
   else 
     -- check for input phase matching gate phase
     if ( (get_phase(A_V,A_T) = gate_phase) and  
	  (get_phase(B_V,B_T) = gate_phase) and
	  (get_phase(C_V,C_T) = gate_phase) and
	   (FI = gate_phase) ) then
       -- we are ready to fire, compute value
      if(MGeneration = TRUE) then
       report_phase("OR301",gate_phase,cycle_number);
      end if;
       cycle_number := cycle_number + 1;
        O_V <= (A_V or B_V or C_V)   after PHASE_DELAY;
       -- compute output phase
	O_T <= lookup_phase((A_V or B_V or C_V),get_phase(A_V,A_T) )  after PHASE_DELAY;
	-- flip gate_phase
	gate_phase := not (gate_phase);
     end if;
   end if;
   FO <= not(gate_phase) after PHASE_DELAY;
   FO_B <= gate_phase after PHASE_DELAY;


end process;
end behavior;

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