* EE 4253/6253 Principles of VLSI Design Laboratory

* Lab 1
* inverter dc & ac simulations

*
* Power supplies
*
v_vcc vcc 0 vccr
v_vss vss 0 vssr

.global vcc vss

*
* Circuit Stimulus
*
*the following line represents a piecewise linear vol. source
*remains at vssr upto 2.5ns and then goes to vccr at 2.6ns -the rise time is 0.1ns
V_in in vss pwl 0ns vssr, 2.5ns vssr, 2.6ns vccr 

*
* Corner information
*
.include '/ecad/local/cadence/cysrc/t/2.0/hp14tb/models/trtc.cor'
.include '/ecad/local/cadence/cysrc/t/2.0/hp14tb/models/tt.cor'
.temp 27
.param vssr=0 vccr=3.3

*
* Options information
*
.options nomod post scale=1e-6

*
* Extra devices
*
.param cload=15e-15
Cl out vss cload

*
* Analysis information
*
.tran 0.01ns 5ns


*measuring the propagation delay for a high to low transition on the output
*since the output goes from high to low, the input must be a low to high transition
*start measuring the time from the instant 'vin' rises to 30% of vccr(final value) to
*the instant when 'vout' falls to 70% vccr.
.measure tran tphl trig v(in) val='0.3*vccr' rise=1 targ v(out) val='0.7*vccr' fall=1
.measure tran Vdd_src param='vccr';
.measure tran Cload_val param='cload';


*
* Circuit include
.include 'inv_sub.sp'


*'.alter' statement format
*uncomment the following lines to include .alter statement
*.alter
*param cload=60e-15
*repeat the above 2 lines for other values of cload

.end