/* This is an example of a .synopsys file that should work for the Xilinx
** 3042PC84-50 part.  Make appropriate modifications to the libraries
** below for other parts; refer to the Synopsys Worldview document
** Application Notes: Xilinx (XC4000) Interface
**
** design_analyzer and dc_shell first read the script
** $SYNOPSYS/admin/setup/.synopsys_dc.setup and then read the
** .synopsys file in the user's home directory or current directory.
*/

search_path = {. \
	/opt/digital/share/xilinx3/xact/synopsys/libraries/syn \
	/opt/digital/synopsys3.2b/libraries/syn}

/* The target architecture libraries include the Xilinx primitives that
** are specific to the 
link_library = {xprim_3042-50.db xprim_3000-50.db \
	xgen_3000.db xdc_3000-50.db}

target_library = {xprim_3042-50.db xprim_3000-50.db \
	xgen_3000.db xdc_3000-50.db}

symbol_library = xc3000.sdb

/* If you mkdir WORK and use the line below, Synopsys will dump its
** compiled modules in that directory.
*/
define_design_lib WORK -path ./WORK

compile_fix_multiple_port_nets = true

bus_naming_style = "%s<%d>"
bus_dimension_separator_style = "><"
bus_inference_style = "%s<%d>"
edifout_netlist_only = true
edifout_power_and_ground_representation = cell
edifout_write_properties_list = "instance_number port_location part"

designer = "Ima Student"
company = "Duke EE"

xnfout_library_version = "5.0.0"