In the previous chapter, we examined the features of VHDL that allow concurrent events to be described. Concurrent VHDL allows you to describe the operation of an inherently parallel system such as a combinational logic network or other digital logic circuit. However, concurrent VHDL does not allow you to clearly specify, at a higher level, what that system is supposed to do over time.
Sequential VHDL statements, on the other hand, allow you to describe the operation, or behavior, of your circuit as a sequence of related events. Such descriptions are natural for order-dependent circuits such as state machines and for complex combinational logic that involves some priority of operations. The use of sequential statements to describe combinational logic implies that our use of the term sequential in VHDL is somewhat different from the term as it is often used to describe digital logic. Specifically, sequential statements written in VHDL do not necessarily represent sequential digital logic circuits. As we will see, it is possible (and quite common) to write sequential VHDL statements, using processes and subprograms, to describe what is essentially combinational logic.
In this chapter we will look at examples of both registered logic and combinational logic described using sequential statements. We will also examine the various types of sequential statements available in VHDL. Our primary focus will be on those styles of sequential VHDL that are most appropriate for synthesizable design descriptions and for test benches. We will also touch on issues related to delay specifications and the order in which processes are analyzed—issues closely related to sequential VHDL.
Sequential statements are found within processes, functions, and procedures. Sequential statements differ from concurrent statements in that they have order dependency. This order dependency may or may not imply a sequential circuit (one involving memory elements).
VHDL's process statement is the primary way you will enter sequential statements. A process statement, including all declarations and sequential statements within it, is actually considered to be a single concurrent statement within a VHDL architecture. This means that you can write as many processes and other concurrent statements as are necessary to describe your design, without worrying about the order in which the simulator will process each concurrent statement.
The general form of a process statement is:
process_name: process (sensitivity_list)
declarations
begin
sequential_statements
end process;
The easiest way to think of a VHDL process is to relate it to event-driven software like a program that executes (in simulation) any time there is an event on one of its inputs (as specified in the sensitivity list). A process describes the sequential execution of statements that are dependent on one or more events having occurred. A flip-flop is a perfect example of such a situation. It remains idle, not changing state, until there is a significant event (either a rising edge on the clock input or an asynchronous reset event) that causes it to operate and potentially change its state.
Although there is a definite order of operations within a process (from top to bottom), you can think of a process as executing in zero time. This means that a process can be used to describe circuits functionally, without regard to their actual timing, and multiple processes can be "executed" in parallel with little or no concern for which processes complete their operations first.
A process can be thought of as a single concurrent statement written within a VHDL architecture, extending from the process keyword (or from the optional process name that precedes it) to the terminating end process keyword pair and semicolon.
The process name (process_name) appearing before the process keyword is optional and can be used to: (1) identify specific processes that are executing during simulation, and (2) more clearly distinguish elements such as local variables that may have common names in different processes.
Immediately following the process statement is an optional list of signals enclosed by parentheses. This list of signals, called the sensitivity list, specifies the conditions under which the process is to begin executing. When a sensitivity list is associated with a process, any change in the value of any input in the list will result in immediate execution of the process.
In the absence of a sensitivity list, the process will execute continuously, but must be provided with at least one wait statement to cause the process to suspend periodically. Examples of processes that are written with and without sensitivity lists are presented in the subsections below.
The order in which statements are written in a process is significant. You can think of a process as a kind of software program that is executed sequentially, from top to bottom, each time it is invoked during simulation. Consider, for example, the following process describing the operation of a counter:
process(Clk)
begin
if Clk = '1' and Clk'event then
if Load = '1' then
Q <= Data_in;
else
Q <= Q + 1;
end if;
end if;
end process;
When this process is executed, the statements appearing between the begin and end process statements are executed in sequence. In this example, the first statement is an if test that will determine if there was a rising edge on the Clk clock input. A second, nested if test determines if the counter should be loaded with Data_in or incremented, depending on the value of the Load input.
When is a process invoked? That depends on the type of process it is. There are two fundamental types of process that you can write: those that have sensitivity lists, and those that do not.
In VHDL Made Easy!, we not only continue with details about processes with and without sensitivity lists, we discuss using processes for registered logic, combinational logic, state machines, and test stimulus. Plus, this chapter includes an extensive section on loops: for loops, while loops, infinite loops, fruit loops... Well, maybe not the latter, but there is a section even Arnold Schwarzenegger might enjoy on loop termination. Believe us when we say: You've never seen anything quite like VHDL Made Easy!