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VHDL Keywords in plain English!

(from VHDL Made Easy!)

Are you tired of seaching for VHDL keyword definitions, only to find that the explanations given are so obscure, they might as well be written in Swahili?

VHDL Made Easy! solves that problem with straight-forward, plain English keyword explanations, complete with examples. And operators are included too. Check out the samples below. References to the appropriate IEEE 1076 Language Reference Manual sections (for example, [LRM 7.2]) are also included.


abs [Operator]:
An absolute value operator which can be applied to any numeric type in an expression. [LRM 7.2]
Example: Delta <= abs(A-B)
access [Keyword]:
Declares an access subtype. Access subtypes are used like pointers to refer to other objects. The objects which an access subtype can reference are array objects, record objects, and scalar type objects. An access declaration includes—in this order—the reserved word "access", followed by a subtype. [LRM 3.3]
Example: type AddressPtr is access RAM;
after [Keyword]
Used in signal assignment statements to indicate a delay value before a signal assignment takes place. A signal assignment statement containing an after clause includes, in this order:
  1. the name of the signal object,
  2. the reserved signal assignment symbol "<=",
  3. the optional keyword "transport",
  4. an expression specifying the value to be assigned to the signal,
  5. the reserved word "after", and
  6. the delay value (of type "time") after which the signal assignment is to take place.
If no after clause is present in a signal assignment statement, an implicit "after 0ns" clause is assumed. [LRM 8.4]
Examples:  Clk <= not Clk after 50 ns;

           Waveform <= transport '1' after 100 ps;        
alias [Keyword]
An alternate name for an object. An alias is primarily used to create a slice (a one-dimensional array referring to all or part) of an existing array. An alias is not a new object, but only an alternate name for all or part of an existing object.
Examples: 

   alias LOWBYTE :std_logic_vector(7 downto 0) is Data1(7 downto 0);

   alias HIGHBYTE :std_logic_vector(7 downto 0) is Data1(15 downto 8); 
Note: aliases cannot be used for multi-dimensional arrays. [LRM 4.3]
all [Keyword]
Used in the following ways:
  1. in a use statement, to make all the items in a package visible,
  2. in an attribute specification, to refer to all the names in a name class,
  3. in a configuration specification (for) statement, to refer to all instances of a component, and
  4. in a signal disconnection specification, to refer to all signal drivers of the same type. [LRM 5.1, 5.2, 5.3]
Examples: use ieee_std_logic_1164.all;

          for DUT: compare use entity work.compare(compare1);
and [Operator]
The logical "and" operator which can be used in an expression. The expression "A and B" returns true only if both A and B are true. [LRM 7.2]
architecture [Keyword]
Defines the internal details of a design entity. An architecture body defines the relationships between the input and output elements of the entity. An architecture body consists of a series of concurrent statements. (An architecture body can also include processes, functions, and procedures, each of which may include sequential statements. Although the statements inside a process, for example, are executed sequentially, the process itself is treated within the architecture body as a concurrent statement.)
A given architecture can be associated with only one entity. However, a given entity may have more than one architecture body.
An architecture statement includes—in this order—the following:
  1. the reserved word "architecture", followed by :
    1. the name of the architecture,
    2. the reserved word "of",
    3. the entity name, and
    4. the reserved word "is",
  2. a declarations section,
  3. the reserved word "begin",
  4. the architecture body (a series of concurrent statements as described above), and
  5. the reserved word "end", followed optionally by the name of the architecture from (1) above. [LRM 1.2]
 Example:

     architecture sample_architecture of compare is	

     begin

          GT <= '1' when A > B else '0';

          LT <= '1' when A < B else '0';

          EQ <= '1' when A = B else '0';

     end sample_architecture;

VHDL Made Easy! includes over 40 pages of keyword definitions and examples just like these.

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