Control flow: Asynchronous controllers

Overview

In this lecture we need to consider:
• How to route the "hot one" control signal from one state element (a latch or flipflop) to the next based on if-then-else, case, and loop statements in VHDL.
• How setting and clearing the state element corresponds to entering and leaving a WAIT statement.
• How to synthesize sequential signal assignments. The statement "sets" a value at the beginning of the next WAIT period, but it is not updated until another sequential signal assignment statement is encountered in the flow of control. This has to correspond to using the "hot one" to clock or latch signal drivers.

General Model

The general model for synthesizing asynchronous WAIT UNTIL is:

The S1 <= wave1 to Sn <= wave_n flipflops shown realize all the sequential signal assignment actions that lie in the VHDL text between the WAIT statement for "current" and the "next" WAIT statement. Note that the new value for all of the signals will not be driven until the "next" state. This corresponds to the VHDL process entering the next WAIT statement.

Block Transfer Controller Example

An example of a VHDL model that can be cleanly realized using this synthesis method is a block data transfer controller that handshakes data across to memory. Note that use of IF-THEN-ELSE and LOOP statements translates cleanly to routing logic to move the "hot" One from flipflop to flipflop.

-- This process involves interfaces to the following other parts of the system
-- CPU
--	cpureq  (may be READ or WRITE)
--	cpu_address
--	cpu_data for WRITE, and returns data to cpu_data on READ
-- Bus Manager
--	may not use the bus until a busreq has been sent and acknowledged
--	with a bus_grant
-- Memory
--	activated with memreq, and responds with a ssyn signal when data is valid
--		on a READ  (nWR = '1'), or when data has been accepted on WRITE
--
process  -- Handshaking for block read or block write
	nWR <= '0';				-- initial conditions
	memreq <= '0';				
	busreq <= '0';				
	msync <=  '0';
	bus_adrs <= (others=>'Z');
	bus_data <= (others=>'Z');
	cpu_data <= (others=>'Z');

	if  (cpureq /= '1') then
		WAIT UNTIL (cpureq = '1');
	
	busreq <= '1';		-- request bus control for block transfer
	-- when granted, assert bus master to preclude any other transfer occuring
	WAIT UNTIL bus_grant = '1';

	while cpureq = '1' loop

			-- Assume CPU does not send cpu_valid until msync='0'
		if cpu_valid = '0' then WAIT UNTIL cpu_val = '1';

		nWR <= not cpu_write;	-- set latches
					-- supply memreq, nWR = '1'
					-- then send msyn after deskewing address
		memreq <= '1';
		msync <= '1' after Tdeskew;   -- issue memory request
		bus_adrs <= cpu_adrs;
		if cpu_write = '1' then
			bus_data <= cpu_data;
		else
			cpu_data <= bus_data;
		end if;
		WAIT UNTIL ssyn = '1';  -- when ssyn is returned

		bus_adrs <= (others=>'Z');
		msync <= '0' after Tskew;

	end loop;

end process;

Basic asynchronous step

1. All signal setting actions take place at the beginning of the WAIT statement following them. There is a flipflop for each state in the circuit above, and the signal that sets each state flipflop also enables the signal assignment actions specified since the preceding WAIT statement.

   Example: For the circuit above, the AND gate that sets S2 flipflop associated with WAIT until ssyn also sets the nWR latch, sets the memreq latch, clocks cpu_adrs to drive bus_adrs, and clocks in the data between the cpu and bus in the direction specified by the cpu_write signal.

2. VHDL sets a driver to a value and that value remains until another sequential VHDL statement sets the driver to a new value. In the circuit above we show the latches that drive memreq and nWR.

   Notice the busreq latch. Because it is reset by the same signal that setsS0 and set by S1 at the same time S0 is reset, it is redundant. Busreq = not S0. The same is true for the msync latch and S3, so it can be optimized out of the circuit, too.

3. If-then-else provides the conditional enabling we need. For example, see the direction control for gating the data in the circuit above.

4. In a loop construct the flow of control is managed by routing the "hot one" through branch control logic.

   For example, the while loop produces the path through AND gate w1 that continues the two step block transfer.

5. Note the RESET at the left edge of the circuit. It is especially important to note how initial values are set in the circuit to correspond to the initial conditions given at the beginning of of process. The RESET through the NOR gates at the bottom of the circuit diagram establish the initial state S0 = "1000". The initial values given at the beginning of the process will then be driven from the output of S0.

6. The expression "IF not C then WAIT UNTIL C" does not require the usual AND gate branching logic when C is a level and the state is to be realized as a latch. Note for the circuit above that we simply feed the C input directly to the set input of the flipflop corresponding to the WAIT if we took the branch. It passes through control immediately just as if we returned from a no delay WAIT.

Rev. 10/13/95 B. Huey