Introduction

Syllabus

Introduction

Background


Applications of Hardware Description Languages

It is important to understand that hardware description languages (HDLs) exist to satisfy a variety of purposes and are used in a number of different ways. Therefore, there are features of VHDL (and any other design language) that will be useless in some applications, and confusing in other applications. Some descriptive features of VHDL may even lead to bad synthesis. A major aspect of this course will be understanding how VHDL should be used to permit synthesis tools to produce good implementations of designs.

To understand why VHDL looks the way it does, it will help to examine the variety of purposes it serves.


Design Specification

Design Documentation


Design Verification

Product Test Generation


Hardware Synthesis


VHSIC Motivations for Creating / Using VHDL


Copyright 1995, Ben M. Huey
Copying this document without the permission of the author is prohibited and a violation of international copyright laws.

Rev. 8/31/95 B. Huey