CSE 518 - Synthesis with Hardware Design Languages
Dr. Ben Huey

E-mail: ben.huey@asu.edu
Phone: 602-965-3699 (voice)

Office Hours

Monday, Wednesday 9:30 - 11:30 a.m.
Thursday 1:00 - 3:00 p.m.

Course Syllabus

Lectures

Introduction and Overview, 8/21
Modeling space and design tools, 8/23
Primitive elements and synthesizable constructs, 8/25

Concurrent constructs and structural equivalents #1, 8/28
Concurrent constructs and structural equivalents #2, 8/30
Behavioral constructs and structural equivalents #1, 9/1

Labor Day -- No class, 9/4

Behavioral constructs and structural equivalents #2, 9/6
Synchronous Controllers: Finite state machines, 9/8

Synchronous Controllers: One hot (Shift) design, 9/11
Asynchronous Controllers, 9/13


There were errors in the material presented 9/13 which have been corrected. The original 9/13 has been replaced with the material presented on 9/25.
Question and answer session. (no lecture), 9/15

Overview of Microcontrollers, 9/18
Overview of Processor Design Process, 9/20
Synthesis with Microcontrollers, 9/22

13 September lecture revisited, 9/25
Introduction to Autologic, 9/27
Combinational synthesis with Autologic, 9/29

Review project #1, Combinational optimization in Autologic, 10/2


No Class, 10/4 Making Autologic work - discussion, 10/6

FSM Synthesis with Autologic, I/O latching, 10/9
FSM Synthesis with Autologic, Styles, 10/11
FSM Synthesis with Autologic, Examples, 10/13

Examination #1, 10/16

Autologic: Arithmetic and relational operations, 10/18
Autologic: Area and performance strategies for Optimization, 10/20

Language level optimizations for Combinational Logic, 10/23
Combinational Optimization: Quine-McCluskey, (DeMicheli, pp. 267-83), 10/25

Combinational Optimization: Espresso Overview, (DeMicheli, pp. 304-10), 10/27

Combinational Optimization: Cover Operations (DeMicheli, pp. 288-294), 10/30
Combinational Optimization: Cover Operations (DeMicheli, pp. 295-303), 11/1
Status reports on Term Projects, 11/3
Status reports on Term Projects, concluded
Combinational Optimization: Algorithms (DeMicheli, pp. 304-10), 11/6
Combinational Optimization: Algorithms (DeMicheli, pp. 310-18), 11/8

Laboratories

Laboratory #1

Modeling and simulation with VHDL: An N-bit Logic Unit. The purpose of this laboratory is to become familiar with the Mentor Design Manager, Design Architect, VHDL compilation and Simulation with QuickVHDL. Reviews concurrent modeling and structural modeling in VHDL.

Laboratory #2

VHDL Synthesis with Autologic: N-bit Logic Unit and CPU-Memory Block Transfer Controller. The purpose of this laboratory is to become familiar with the Sys1076 VHDL compiler and Autologic. Introduces ideas of optimization for area and speed, separation of asynchronous design into multiple processes for synthesis.

Final Project

Option #1: Range Protection Lookaside Buffer

Option #2: Microsequencer

Option #3: Data Unit

Reference materials:

Interesting Links

VHDL International Users' Forum

VHDL Synthesis Working Group

VLSI Related Research Institutions

Rev. 10/12/95 B. Huey