CSE 518 - Synthesis with Hardware Design Languages
Catalog Description
Modeling VLSI designs in hardware design languages for synthesis. Transformation of language-based designs to physical layout. Application of synthesis tools.
3 lectures & lab. Credit: 3 hours
Prerequisite: The normal prerequisite is CSE 517. For this semester that
prerequisite is being waived, but with the understanding that students will
be responsible for learning language syntax and programming pretty much on
their own. We will continue to emphasize the application of VHDL to synthesis.
Textbook
Chang, K.C.,
Digital Design and Modeling with VHDL and Synthesis. IEEE Computer Society
Press, 1997.
We will also use Web notes, course handouts, online documentation for tools.
Coordinator
Ben M. Huey, Associate Professor
Goals
- Ability to develop high level behavioral designs that are readily synthesizable.
- Understanding of the translation process from a HDL (like VHDL) into actual semiconductor implementations.
- Some appreciation of design / implementation tradeoffs in the synthesis process.
- Some experience using commercially available synthesis tools.
Prerequisites by Topic
- Experience writing and simulating moderately sized VHDL models.
- Formal understanding of digital logic design principles for combinational and sequential circuits.
- Understanding of semiconductor device theory.
- Understanding of language design principles: iteration, recursion, parameteriation, concurrency, data structures.
- Introductory understanding of graph theory.
Introduction
This course is intended for those interested in computer engineering and
who have a good background both in combinational and sequential logic design
and in computer organization. Students are expected to know how to write and
debug reasonably sized software projects and should have some experience with
simulation before taking this course.
In this course we focus on the translation process using cells and templates to create physical layouts, and the consequences of using different
organizational structures, technologies, and binding rules.
The course includes three small laboratory projects and a major team project.
Topics
- Concurrent and behavioral VHDL constructs and structural equivalents
- Methods for synthesis of control constructs: from state machines to microcontrol engines
- Timing, latching techniques
- Design tradeoffs: modularity, power, speed, size
- Resource allocation and scheduling
- Group design projects and critiques
Total Credits
3 Units
Rev. 11/26/97 B. Huey