CSE 518 Final Project - Intel 8051

Students are to organize themselves into teams. The parameters are:

  1. Teams of 4-6 members.
  2. At least one member of each team must be from a remote site, and at least one member must be from on-campus.
  3. You will need to consider the synthesis environment you want to use early on. Synopsys is OK, but you will have to work out the logistics for your group.
  4. Submit your project preference to me. I expect to need to "broker" team memberships simply because we are a distributed class.

Your design is not expected to model and synthesize the entire 8051 in the brief time available yet this semester. However, by partitioning the design across the team and making effective use of the synthesis tools available, you should be able to produce an "80%" design. It is not necessary to fully model the entire instruction set. However, by properly abstracting the essential features of the instructions (addressing modes, instruction classes, etc.) the result should generate nearly all of the hardware. You are expected to implement a timer, the serial port, and support at least part of the interrupt structure of the 8051. The design is also to include Ports 0-3. You are not required to implement the ROM/EPROM. If you find it necessary to modify the RAM specification, get approval from me first.

For more detailed information about the 8051, you may wish to check the following sites:

Intel Literature

MCS 51 Datasheet (762kb, PDF format)


Copyright 1997, Ben M. Huey
Copying this document without the permission of the author is prohibited and a violation of international copyright laws.
Rev. 2/20/97 B. Huey