CSE 591 Hardware Synthesis with VHDL
Examination #1

I. (15 pts.) Sketch schematics for the following constructs. Unless specified otherwise, assume signals of type std_logic or std_logic_vector of the appropriate size.

      SIGNAL enable : std_ulogic;       
      SIGNAL a, b : boolean; 
      SIGNAL X, Y, Z : std_logic;

 
a.   IF enable = '0'   
      THEN Y <= X;                                                           
      END IF;






b.   IF enable = '1'   
      THEN Z <=  X;
      ELSE  Z <= Y;
      END IF; 






c.   IF a OR b
      THEN Z <= X; 
      ELSIF  a AND b   
            THEN Z <= not X;  
            ELSE   Z <= Y;  
      END IF; 















II. (15 pts.) Sketch schematics for the following constructs. Unless specified otherwise, assume signals of type std_logic or std_logic_vector of the appropriate size.

a.  IF  enable = '1'       
    THEN Z <= X;   
    ELSIF enable = '0' 
        THEN  Z <= not X;   
        ELSE Z <= 'X';
    END IF;                                                                     
Z < = 'X' is not used by the synthesis tool. You may also recognize the circuit above can be replaced by XNOR.

EVERYONE GETS 5 FREE POINTS FOR PART B. The question shown below is the one intended, and the solution is shown on the right.

b. IF  sel = "00"
    THEN  Y <= X;   
    ELSE Y <= 'Z';                                                        
    END IF;     
    IF  sel = "01" and a   
    THEN  Z <= X;   
    ELSE Z <= Z';  
    END IF;                                                                         

c.  SIGNAL p : integer range 0 to 3; 
    SIGNAL Y : std_logic_vector(0 to 1);
     
    CASE p IS 
    when 0 => Y <= "10" after Tprop;  
    when 1 => Y <=   X   after Tprop;  
    when 2 => Y <=   Y   after Tprop;  
    when 3 => Y <= "01" after  Tprop;  
    END CASE;                                                                     


III. (15 pts.) Sketch schematics for the following constructs. Unless specified otherwise, assume signals of type std_logic or std_logic_vector of the appropriate size. Indicate clearly whenever you are showing buses what the width and connection is.

a.  WITH regsel SELECT  
    Z <= A after Tprop WHEN "00"   
        B after Tprop WHEN  "01"   
        C after Tprop WHEN "10"   
        D after Tprop WHEN "11"  
        "XX" after Tprop WHEN others; 

b.   SIGNAL  pbus : std_logic  BUS;                            
    a1:  BLOCK  ( enable = '0' )   
        pbus <= guarded X after Tprop;   
        END BLOCK a1;                                                
    a2:  BLOCK  ( enable = '1' )   
        pbus <= guarded Y after Tprop;   
        END BLOCK a2;                                                
c.  SIGNAL Z : std_logic_vector( 0 to 2) BUS;  
    SIGNAL X, Y : std_logic_vector( 0 to 2);  
    SIGNAL a, b : std_logic;  

    a0:  BLOCK  ( a = '1')  
        Z <= X after Tprop;                                                
        END BLOCK;   

    a1:  BLOCK ( b = '1')  
        Z <= Y after Tprop;  
        END BLOCK;                                                            

IV. (15 pts.) How does a synthesis tool use each of the following pieces of information:

a. SIGNAL x : 0 to 63;

	Signal X is either a bus or a register of 6 bits.  

b. CONSTANT xxxs : std_logic_vector (0 to 7) := (others => 'X');

	XXXs represents "XXXX_XXXX" which is useful for simulation, 
            but not for synthesis.
c. SIGNAL Y : std_logic_vector ( X'range ) BUS;
d. ASSERT clock'event and clock = '1' and J'stable(3 ns) and K'stable(3 ns) e. Z <= X(N-1) & X( 0 to N-2) -- X(0 to N-1)

V. (15 pts.) Sketch the unoptimized circuit (4 pts.) and then explaining your steps transform the original circuit into an optimized result. (4 pts).

a.  Y := X(0);    
    FOR i in 1 to 3 LOOP    
        IF X(i) = '1' THEN Y <= not Y;    
    END LOOP;    
Vb. SIGNAL Y : std_logic_vector (0 to 3);    
    SIGNAL opcode : std_logic_vector (0 to 1);    

    WITH  opcode SELECT     
    Y <= "0001" WHEN "11",    
        "0010" WHEN "10",    
        "0100" WHEN "01",    
        "1000" WHEN "00";    
VI. (15 pts.) Given the following state transition diagram, write a VHDL description that separates the clock, the next state logic, and the output function into separate processes. Use an enumerated type for the state object.

VI.b. Draw a schematic (using D flipflops) similar to the circuit that either Synopsys or Autologic should produce from such a description. Assume a "one hot" encoding of the states.

VII. (10 pts.) Asynchronous design

Even though Synopsys and Autologic won't synthesize this description, using the form using a "one hot" encoding of the implicit states developed in class this semester to support the representation of algorithmic state machines (flowchart approaches to describing state machines), what should a synthesis tool produce?

    ARCHITECTURE a OF b IS  
    SIGNAL  request, send,  ack : boolean;  
    SIGNAL  Data_in, Cvec : std_logic_vector (0 to 3); 
    BEGIN

    PROCESS BEGIN  
        send <= false;  
        WAIT UNTIL request;  
        send <= true;     
        Cvec <= Data_in;  
        WAIT UNTIL ack; 
        END PROCESS;    
    END a;                                            

Copyright 1995, Ben M. Huey
Copying this document without the permission of the author is prohibited and a violation of international copyright laws.

Revised 12/11/95