EE295 - ASIC Design Using VHDL

Verification Survey

Assignment: Selected Readings in the Verification Field

• "VITAL 102: An Update", Steven Schulz, ASIC&EDA, May 1994
• "Simulating at High Levels Shows Promise", Lisa Malnuiak, Electronic Design, March 18, 1993
• "Putting it Together: Prototyping Methods", R T "Tets" Maniwa, Antegrated System Design, September, 1995
• "Ready for Prime Time", Steven Schulz, Integrated System Design, April 1995

ASIC Technology is today breaking the mega-cell barrier - a million library cells designed and produced as a single entity. It is a commonly accepted fact that in this environment a previously overlooked factor, interconnect delay, now accounts for up to 75% of the total delay in a design. Predicting, controlling and measuring interconnect delay is now the focus of most submicron ASIC methodologies. In this class we'll examine some of the current strategies for design verification that deal with high data volumes and interconnect delays.

Outline:

• Verification Spectrum
• IEEE Packages
• Interpretive vs Compiled Technology
• VITAL
• Cycle-Based Simulation
• Hardware Accelerators
• Prototyping with Field Programmable Devices
• Parallel Simulation
• Boolean Equivilance
• Timing Analysis

Verification Spectrum

• Structure:
  • Purely Behavioral
  • Register Transfer Level
  • Gate Level - Netlist
    • Often Source of Manufacturing Test Patterns
    • WAVES, TSSI
  • Gate Level Annotated Technology Specific Information
    • Resistance
    • Capacitance
    • Placement
    • Cell Power Level
• Performance:
  • No Delay Information
  • Estimated Delays as a Function of
    • Nothing - Some Nominal Value
    • Load/Fanout
    • Transition Time
    • Area
    • Operating Voltage/Temp
  • Actual Delays
    • Parasitic Information Extracted from Physical Design Model via Physical Delay Exchange File ( PDEF )
    • Delay Information/Timing Rule Checks via Standard Delay File ( SDF )

IEEE Packages

Interpretive vs Compiled

VITAL

• VHDL Initiative Toward ASIC Libraries
• Attempt to Encourage Foundries to Produce VHDL Cell Libraries
• Prior to VITAL Library Portability was a Real Issue
• Foundries Provide a Simulation Library Consisting of
  • Components Package
  • Entities With Generics Using a Prescribed Naming Scheme
  • Architectures Constructed from VITAL Primitives Package
  • Standard Delay Files ( SDF ) at Various Stages in Design Processing
• Synthesis Tool Vendors Must Provide Ability to Export a VHDL Netlist, a Gate-Level VHDL Representation ( or All Component Instance Representation ) of the Design.
• Simulation Tool Vendors Must Provide Ability to Read in SDF and Attach the Delay Information to the Generics at the Cell Entities. Accelerate the VITAL Primitives.

Cycle-Based Simulation

• Not a VHDL Simulation Environment

Hardware Accelerators

Prototyping with Field Programmable Devices

• With HDL and Synthesis You're Able to Create an FPGA netlist While you Wait for the Foundry to Make Your Product
• This Inexpensive Programmable Device can be Used on a Prototype Breadboard of Your Product Allowing Verification of Function but Not Performance
  • And Allows you to Submit Engineering Changes to the Foundry Before Final Product Personalization
  • Finding it's Way Into a lot of Final Products

Parallel Simulation

Boolean Equivilance

Static Timing Analysis