EE295 - ASIC Design Using VHDL

Sequential Processing

Assignment:

• Read Ch 3
• Explain in your own words what is wrong with the 'incorrect' mux on pg 41.

 We discuss Sequential Processing, basically the use of contemporary
programming practices to effectively model system behavior. The
System is, of course, not limited to CMOS ASIC Chips. Fiber Optic
Channels, Satelite Uplinks, LANs.. These are the building blocks
of some of today's systems. In this environment accurate electrical
modelling is compromised for powerful forms of expression: Complex
Data Structures and Algorthmic Proccessing.

VHDL includes a structured programming language and a clean,
well-disciplined interface between the concurrent environment and
the sequential environment.

Outline

• What is Sequential Processing
• Signal Evaluation vs Variable Assignment
• Signal Assignment Within a Process
• The Process Statement
• The Assert Statement
• Sequential Statements:
  • If
  • Case
    • Null
  • Loop
    • Next/Exit
  • Wait
  • Return

What is Sequential Processing?

• Appear in Processes and Sub-Programs
• Statements are Executed in Order
• Variables are Assigned Values
• Mathematic Operators
• Time Does Not Increment! Not Even Delta Time!
• Must Indicate What Signals Activate the Process

Signal Evaluation vs Variable Assignment

• Signals model real electronic circuit behavoir more accurately

   but
  

• To Do So Carries More Processing Overhead for Simulation
• Variables are More Efficient Models of Abstract Behaviour

   but
  

• Compromise Real Circuit Modeling

Concurrent Signal Assignment Problem

• Signal Assignments May Appear in a Process
• However the Results May be Confusing
• Because Time Does Not Increment
  • Values are Placed on the Driver List
  • But Never Take Place Until the Process Halts and Time Moves On
  • But You Legally May have Referred to that Signal in the Process. What did you get? Uninitialized Garbage?

Process

• Actually a Concurrent Statement! Appears in the Body of an Architecture.
• Delimits a Section of Sequential Code
• Optional Sensitivity List Indicates Which Signals 'Wake Up' a Process
• Self-Contained Declarative Region
• Important Time Does Not Increment in a Process - Not Even Delta Time!! Signal Assignments Don't 'Take Place' Until The Process Suspends.

Assert Statement

• Means of Communicating Important Information about the Status of a Design in the Simulation Environment
• Ignored by Synthesis Tools - But May Indicate Potential Hardware Failure. A Design That Shouldn't be Synthesized.
• Assert condition [Report string] [Severity level]
  • condition Must Evaluate to a Boolean Condition
  • When it is False the Statement Executes
• Report string
  • string is the Message to be Passed to the Designer
  • "Signal has Multiple Drivers With Different Values"
  • "Data Arrived Late"
  • Defaults to "Assertion violation."
• Severity level - One of:
  • Note
  • Warning
  • Error
  • Failure - Simulation Ceases Execution

Sequential Statements

• IF

        if condition then
             statements...
           [elseif condition
             statements...]
           [else
             statements...]
           end if;
  

• CASE

         Case exp is
              when choice => statements..
                  ...
              [others statements..;]
              end case;
  

  • choice Indicates a Value the Expression May Take On
  • All Possible Choices Must be 'Covered'
  • Use of others Simplifies This
    • null; -- do nothing quickly
    • Often When Applying 'Others' The Desire is to 'Do' Nothing - Hence the Null;
  • So Can Use of a Sub-Type to Constrain the Choices
• LOOP

  [label:][iteration scheme] loop condition
  

  • Where iteration scheme may be:
    • while condition
    • for identifier in range
      • Identifier is Self-defining
      • Visible Only in the Loop
      • Range Specifications:
        • i in 0 to 7
        • letter in ( 'A', 'B', 'C')
        • j in 7 downto 0
  • And the Following Statements May Alter the Loop Flow:
    • next - Skip Execution of Following Statements and Iterate Loop
    • exit - Terminate Execution of the Loop
• WAIT - Halt Process Execution
  • wait on [condition]
  • wait until [condition]
  • wait for [condition]
• RETURN [expr]
  • Indicate the Value a Function Returns.