EE295 - ASIC Design Using VHDL

Asic Methodology

Assignment: n/a

 We discuss the ASIC Design Methodology or Process.
The steps needed to design an ASIC.

Outline

• A Simple Methodology
• A Complicated One
• Our Methodology
• Design Steps:
  • Project Definition
  • Design Capture
  • Simulation
  • Synthesis
  • Verification
  • Test
  • Physical Design

A Simplified Methodology

Our Methodology

Documentation for These Products is now available
on the web. Take some Time to Familiarize Yourself with AUSSIM and Booledozer
and HIS.

Design Steps:

Project Definition

• Define Project Goals
• Call Banker
• Decompose the Design into Building Blocks
• Estimate Size of Design Task
• Select a Technology. Negotiate Schedules/Prices. Discuss Methodology.
• Compose Design Tool Suite, HDL
• Call Banker Back

Design Capture

• Preparing a Design
• In Addition to Product Function Some Technology Specific Information, In the Form of Component Instances and Attributes Usage is Usually Inevitable at This Phase.
• Usually Done in Favorite Text Editor
• Some Editors Have Key Bindings to Assist with Syntax ( eg. emacs, epoch )
• Growing Collection of Specialized Design Capture Tools
  • State Editor - Describe Finite State Machines ( FSMs ) with State Diagrams
  • Schematic Capture - Schematically Describe System Architecture & Interconnection but Export VHDL
• Prepare a Design and the Testbench to Exercise it.

Simulation

• Purpose:
  • Analyze a Design/Testbench for Correct Syntax
  • Elaborate the Design for Integrity
  • Run the Testbench and..
  • ..Observe that the VHDL Behaves as Expected.
• Design Environment:
  • Foundry:
    • Technology Components Package for the Cell Library
    • Entity/Architecture(s) Representing Cell Behavior
    • VITAL is a Standardization of the Above
    • Custom Macro Behaviorals
  • Vendor:
    • IEEE Packages ( See Appendix A )
    • Optional Utility Packages
      • Conversion Functions
      • 'Smart Models' Compiled Macro Behaviorals Optimized for Simulation Performance
      • Newest Language Revision Permits 'Foriegn' Interface
  • Designer:
    • Package(s) Containing Common Constants, Functions, Types, Macro Components
    • Initialization File Indicating:
      • Association of Physical Directories to VHDL Libraries Containing Packages
      • Previous State of Simulation Windows
      • Trace File Name
      • Vendors Provide an Alternative Control Language Routinely Enabling Stimulion of Inputs and Observation of Outputs, Loading of Pattern Files, etc.
      • But..
      • These are Not Portable to Other Simulator Products/Versions - VHDL TestBenchs Are
      • Latest Language Enhancement will Enhance File Interface Improving TestBench Performance

Synthesis

Note: VHDL CAD Products Seldom Share an Internal Database.
It is Often Necessary to Analyze Your Design into Every CAD Product
Involved in the Methodology. Even More Challenging, Whereas Most
Commercially Successful VHDL Simulation Products Handle 99%+ of the
Language, Synthesis Tools are not as Mature. Currently, There is
Preliminary Standardization Work Initiating in This Area.

• Purpose
  • Translate Your Design Containing Mix of Abstract/ Dataflow/ Component Representations and
  • Produce an Optimal Technology Specific Netlist
• Process
  • Re-analyze the Design
  • Establish Goals:
    • Area - Based on
      • Non
      • Absolute Minimum
      • Die Size Constraints
      • Floorplan
    • Performance - Based on
      • Market Expectations
      • 'Paper Analysys' Using Technology Databook
      • New Generation of Architectural Evaluation Products - 'Quickie Synthesis'
    • Performance - Expressed in
      • Cycle Time(s) = Clock Period
      • Actual Arrival Times of Inputs
      • Desired Arrival Times of Outputs
  • Examine Results
    • A Synthesis Tool Comes to Successful Completion Regardless of
      • Attaining Performance/Area Objectives
      • Rendering the Best Possible Design
• Design Environment:
  • Foundry
    • Representation of the Cell Library:
      • Cell Names, Pins
      • Function
      • Area
      • Delay ( Note - This is Sensitive Information )
      • Drive Capacity
      • Power
    • Delay Reports Reflecting
      • More Accurate Delay Modelling
      • Estimated/Actual Delays Based on Partial/Complete Physical Design
    • Vendor:
      • IEEE Packages ( See Appendix A )
      • Optional Synthesis-Oriented Utility Packages
        • Don't Touch My Net, Component, Port, Expression
        • Cell Hint on Targetting to a Technology Cell
        • Other Keywords That Are Intended to Be Passed Along to Other CAD Tools Through Netlist
        • Capacitance Targets for PD, Test Signals for Test Pattern Generation ( ATPG )
        • Attributes are the Usual Mechanism
        • Functions That Influence the Results of Synthesis Mapping
    • Designer:
      • Package(s) Containing Common Constants, Functions, Types, Macro Components
      • Initialization File Indicating:
        • Location of Foundry/Vendor Files
        • Output Technology Specific Netlist ( usually EDIF ), Side Files
      • Control Script Executing Design-Specific Steps

Additional Verification

• Even Though We've Verified Our VHDL's Function Before Synthesis
• Commonly Accepted Practice is to Verify the Design at a More Technology Specific Representation Using a Library Provided by the Foundry.
• VITAL Standard Focused on this Area Using VHDL Netlists Output by the Synthesis Product + 'acceleratable primitives' for Library Model Construction.

Test

Many Diverse Strategies Ranging From:

• Designers Producing
  • Functional Simulation Vectors - Usually Insufficient
  • Additional Fault Detection Patterns Coded by Designer
  • Automatic Generation of Test Patterns ( Call Banker - ATPG Software isnt Free)
  • Built-In Test Generation Macros Inserted in Your Design
• Foundry/Consultant Assistance With
  • Additional Fault Detection Patterns Coded by Designer
  • Automatic Generation of Test Patterns
  • Built-In Test Generation Macros Inserted in Your Design

Physical Design

• Importing Your Design Files into the Foundry CAD Environment
• Remaining Foundry Specific Customization
  • Construction of Optimal Clock and Reset Distribution Networks
  • Insertion of Proprietary Macro Representations ie. RAMs, ALU's
  • Insertion of Test Macros
• Foundry Confirms That Design Meets Performance Objectives Before Proceeding
• Designer Confirms That Updated Netlist Still Meets Performance and Function Objectives
• Placing the Design Objects on an Image or Representation of the Available Silicon Die Area
• Re-Evaluation of Results WRT Original Product Performace ( Delay ) Objectives While Estimating the Effects of Wiring
• Wiring or Electrical Interconnection of Design Objects WRT Physical Placement
• Re-Evaluation of Results WRT Original Product Performace ( Delay ) Objectives With Maximal Accuracy
• Photolithographic Masks are Prepared to Mass Produce Your Design