-- counter.vhd                     J Swift/ IBM Corp/ copyright 1995
-- generic counter process

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

Entity counter is
  Port ( reset, enable, clock : in  std_logic;
         count       : out std_logic_vector ( 0 to 11 ) );
end;

Architecture behavioural of counter is

signal int_count : unsigned ( 0 to 11 ) := "000000000000";

begin
  process ( reset, enable, clock )
    begin
    if ( reset = '0' ) then                     --reset
      int_count <= "000000000000";
    elsif ( reset = '1' and enable = '0' ) then     --noop
      int_count <= int_count;
    elsif ( enable = '1' ) then
      if ( clock = '1' and clock'event ) then        --increment
        int_count <= int_count + 1;
      end if;
    end if;
  end process;

count <= conv_std_logic_vector( int_count, 12 );

end behavioural;