1. Outline:Introduction, Organization, Outline

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2. Design_Environments: Digital system design process, Hardware description languages, Hardware simulation, Hardware synthesis

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3. VHDL_Background: VHDL initiation, Existing languages, VHDL requirements, The VHDL language, VHDL based design process, Levels of abstraction

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4. VHDL_Overview: Behavioral description, Using process statements, Top-down design, Using available components, Wiring predefined components, Wiring from bottom to top, Generation of testbench data, Using procedures

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The Class notes are copyright © by Dr. Zainalabedin Navabi, Art work for the notes has been done by Fatekeh Asgari, asgari@khorshid.ut.ac.ir, and Web pages have been developed by Funda Kutay.
Last modified August 8, 1996. Funda Kutay is in charge of this page, funda@ece.neu.edu, Under provision of: Prof. Zainalabedin Navabi, navabi@ece.neu.edu